Phase and frequency digital synchronizer

An apparatus comprising:

• a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal;
• a memory element to store the values of the output information;
• a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information;
• and
• circuitry to generate the control information based on conditions determined at least from the values stored in the memory element, wherein the circuitry is to generate correction information based on a current value of the output information and a previous value of the output information, the circuitry is to adjust a value of the digital code based on the correction information, and the circuitry is to increase a value of the correction information if the current value of the output information and at least one of previous values of the output information have a same value.

An apparatus comprising:

• a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal;
• a memory element to store the values of the output information;
• a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information;
• and
• circuitry to generate the control information based on conditions determined at least from the values stored in the memory element, wherein the circuitry is to generate correction information based on a current value of the output information and a previous value of the output information, the circuitry is to adjust a value of the digital code based on the correction information, and the circuitry is to decrease a value of the correction information based on a condition determined from the current value of the output information and at least one of previous values of the output information.

An apparatus comprising:

• a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal;
• a memory element to store the values of the output information;
• a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information;
• and
• circuitry to generate the control information based on conditions determined at least from the values stored in the memory element, wherein the circuitry is to generate correction information based on a current value of the output information and a previous value of the output information, the circuitry is to adjust a value of the digital code based on the correction information, and, wherein the circuitry is to decrease a value of the correction information if the current value of the output information and at least one of previous values of the output information have different values.

An apparatus comprising:

• a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal;
• a memory element to store the values of the output information;
• a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information;
• and
• circuitry to generate the control information based on conditions determined at least from the values stored in the memory element, wherein the circuitry is to compute values for proportional control rate information and integral control rate information before decoding the values to generate additional values for calculating the value of the digital code.

An apparatus comprising:

• a pulse-width modulator (PWM) included in a voltage controller to generate a PWM signal;
• and
• a synchronizer included in the voltage controller to generate an output clock signal and provide the output clock signal to the pulse-width modulator as part of generation of the PWM signal, the synchronizer including:
• a phase frequency detector to generate output information based on a relationship between a first clock signal and a second clock signal;
• a digital controlled oscillator to generate the second clock signal;
• circuitry to generate a digital code based on correction information to control the phase and frequency of the second clock signal, the correction information being generated based on a condition determined from at least a first value and second value of the output information, the first value being generated based on a first relationship between the first and second clock signals, the second value being generated based on a second relationship between the first and second clock signals.

An apparatus comprising:

• an antenna;
• and
• an integrated circuit device coupled to the antenna, the integrated circuit device including a voltage regulator, the voltage regulator including a pulse-width modulator, the pulse-width modulator including a frequency synchronizer, the frequency synchronizer including:
• a phase frequency detector to generate output information at an output of the phase frequency detector, the output information having a value based on a relationship between a first clock signal and a second clock signal;
• a memory element to store the values of the output information;
• a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information;
• and
• circuitry to generate the control information based on conditions determined at least from the values stored in the memory element.