Bridged integrated circuits
OwnerJonathan Rossinventor
Life of this patent
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Abstract
Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.
Claims19
A system comprising:
- a first integrated circuit chip comprising application logic for one or more executable applications;
- and
- a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip comprising:
- an instruction decoder configured to decode instructions for executing the one or more executable applications;
- and
- a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip,
- wherein the decoded instructions are executed in a deterministic manner such that each decoded instruction is executed at a respective predetermined timing.
A computer-implemented method, comprising:
- obtaining, by a FPGA, instructions for executing one or more executable applications stored in an ASIC;
- decoding, by the FPGA, the instructions for executing the one or more executable applications;
- transmitting, from the FPGA to the ASIC, the decoded instructions and input data for the one or more executable applications;
- executing, by the ASIC and based on the decoded instructions and the input data, the decoded instructions to execute the one or more executable applications to generate output data;
- and
- transmitting, from the ASIC to the FPGA, the output data,
- wherein the decoded instructions are executed in a deterministic manner such that each decoded instruction is executed at a respective predetermined timing.
A method for executing an executable application on an ASIC, the method comprising:
- receiving, from a FPGA and by an ASIC, data representing (i) decoded instructions, (ii) input data for executing one or more executable applications that are stored in the ASIC, and (iii) memory locations for storing the decoded instructions and the input data;
- storing, by the ASIC, the decoded instructions and the input data at the memory locations;
- obtaining, by the ASIC, the decoded instructions and the input data from the memory locations;
- executing, by the ASIC and based on (i) the decoded instructions, (ii) the input data, and (iii) application logic for the one or more executable applications to generate output data;
- and
- transmitting, from the ASIC to the FPGA, the output data.
Dependencies are inferred from the claim text.