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US 10,374,604 B1Granted
Dynamic decode circuit low power application
AssigneeInternational Business Machines Corporation
InventorAntonio Raffaele Pelella
Life of this patent
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Abstract
A dynamic decode circuit for decoding a plurality of input signals to produce a positive output pulse one gate delay following a clock signal, wherein the output pulse indicates the plurality of signals were all positive, wherein the output pulse is active during an evaluation phase of a clock cycle and not active during a precharge phase of the clock cycle, wherein precharge is performed by nfet transistors.
Claims20
A dynamic logic circuit comprising:
- a dynamic decode logic circuit comprising one or more nfet precharge circuits connected to a first power source, wherein each of the nfet precharge circuits comprises a first nfet precharge transistor having a first nfet precharge gate configured to receive a negative active evaluation clock signal, wherein the negative active evaluation clock signal is configured to be low during an evaluation phase;
- wherein the dynamic decode logic circuit further comprises one or more pfet evaluate transistors connected to a second power source, wherein each of the pfet evaluate transistors has a first pfet evaluation gate configured to receive the negative active evaluation clock signal;
- wherein the dynamic decode logic circuit further comprises a decoder, wherein the decoder is configured to decode a plurality of inputs to pull a first node to a low state based on the plurality of inputs being in a predetermined state, wherein the decoder is configured to not pull the first node to the low state based on the plurality of inputs not being in the predetermined state;
- wherein the dynamic decode logic circuit further comprises an evaluation circuit, the evaluation circuit consisting of a first nfet transistor serially connected to a first pfet transistor by a second node, wherein the first pfet transistor comprises a first pfet gate conductively connected to the first node, wherein the first nfet transistor comprises a first nfet gate conductively connected to the first node, wherein the first pfet transistor is connected to a pfet evaluate transistor by a pfet share (PSHARE) node, wherein a first nfet precharge circuit is configured to precharge the first node to the low state during a precharge phase of the negative active evaluation clock signal;
- and
- wherein the dynamic decode logic circuit further comprises a third node of the decoder conductively connected to a pfet evaluate transistor.
3 more elements
Dependencies are inferred from the claim text.