Back to results
US 10,374,602 B1Granted
Transistor linearization techniques
AssigneeAnalog Devices, Inc.
InventorOmid Foroudi
Life of this patent
Estimating the term…
Abstract
Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.
Claims20
A circuit for linearizing an adjustable resistance of a field effect transistor (FET), the circuit comprising:
- the FET;
- and
- a differential amplifier configured to apply a representation of a voltage of a drain of the FET and a representation of a voltage of a source of the FET to a gate of the FET by mixing the representations at a common node different from the drain and the source and applying the mixed representations as an input of the amplifier.
A circuit for linearizing an adjustable resistance of a field effect transistor (FET), the circuit comprising:
- the FET;
- a differential amplifier configured to apply a representation of a voltage of a drain of the FET and a representation of a voltage of a source of the FET to a gate of the FET;
- a first resistor configured to couple the source to a first input of the amplifier;
- a second resistor configured to couple the drain to the first input of the amplifier;
- and
- wherein an average voltage of the voltage of the drain and the voltage of the source provides the representation of the voltage of the drain and the representation of the voltage of the source.
3 more elements
A method for linearizing a Field Effect Transistor (FET), the method comprising;
- coupling a first signal at a source node of the FET to a first input of a differential amplifier via a first resistor;
- coupling a second signal at a drain node of the FET to the first input of the amplifier via a second resistor;
- averaging a voltage of the first signal with a voltage of the second signal via the amplifier to provide an average voltage;
- and
- applying the average voltage to a gate node of the FET.
2 more elements
Dependencies are inferred from the claim text.