Back to results
US 10,374,584 B1Granted
Low power retention flip-flop with level-sensitive scan circuitry
AssigneeIntel Corporation
InventorsCharles Augustine, Muhammad Khellah, Arvind Raman, Feroze Merchant, Ashish Choubal
Life of this patent
Estimating the term…
Abstract
An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.
Claims19
An apparatus comprising:
- a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail;
- and
- a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail, wherein the scan circuitry comprises an inverter connected to the slave stage, wherein the inverter is controllable by a scan signal, and wherein the inverter is coupled to the second power supply rail.
An apparatus comprising:
- a flip-flop;
- and
- a scan circuitry coupled to the flip-flip, wherein the scan circuitry is to retain data from the flip-flop when the flip-flop is in low power state, wherein the scan circuitry comprises an inverter connected to a slave stage of the flip-flop, wherein the inverter is controllable by a scan signal, and wherein the inverter is coupled to a power supply rail separate from a power supply coupled to the flip-flop.
A system comprising:
- a memory;
- a processor coupled to the memory, wherein the processor includes a sequential circuitry including:
- a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail;
- and
- a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail, wherein the scan circuitry comprises an inverter connected to the slave stage, wherein the inverter is controllable by a scan signal, and wherein the inverter is coupled to the second power supply rail;
- and
- a wireless interface to allow the processor to communicate with another device.
4 more elements
Dependencies are inferred from the claim text.