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US 10,374,574 B2Granted
Method of providing protective cavity and integrated passive components in wafer level chip scale package using a carrier wafer
AssigneeSkyworks Solutions, Inc.
InventorJoseph Michael Bulger
Life of this patent
Estimating the term…
Abstract
A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate.
Claims24
A wafer-level chip-scale package comprising:
- a polymeric body having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via;
- a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate;
- and
- a seal ring including metal disposed in the body and having an upper end directly bonded to the piezoelectric substrate.
1 more element
A wafer-level chip-scale package comprising:
- a polymeric body having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via;
- a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate;
- a metal roof disposed on an upper surface of the body and defining a lower surface of the cavity;
- and
- metal standoffs disposed between the metal roof and the piezoelectric substrate.
2 more elements
A wafer-level chip-scale package comprising:
- a polymeric body including polyimide having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via, the body including two layers of polymer and a dielectric layer disposed between the two layers of polymer;
- and
- a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate.
A wafer-level chip-scale package comprising:
- a polymeric body having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via;
- a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate;
- a metal roof encapsulated in a dielectric and disposed on an upper surface of the body below the cavity;
- and
- metal standoffs disposed between the dielectric and the piezoelectric substrate.
2 more elements
Dependencies are inferred from the claim text.