Circuit and method for electrostatic discharge clamping

A circuit for electrostatic discharge clamping, comprising:

• a detection module coupled with a first power line of a first power source and a second power line of the first power source, wherein a third terminal of the detection module is coupled to a first power line of a second power source;
• a control module coupled with the first power line of the first power source and the second power line of the first power source, wherein a third terminal of the control module is directly connected to a voltage division terminal of the detection module, wherein the control module comprises two inverters respectively connected between the first and second power lines of the first power source, the two inverters respectively comprising a first pair of transistors with opposite polarities and a second pair of transistors with opposite polarities, gates of the first pair of transistors serve as the third terminal of the control module, and drains of the first pair of transistors are directly connected to gates of the second pair of transistors;
• and
• a clamping module coupled with the first power line of the first power source and the second power line of the first power source, wherein a third terminal of the clamping module is directly connected to a fourth terminal of the control module, wherein drains of the second pair of transistor serve as the fourth terminal of the control module;
• wherein the voltage division terminal provides a voltage to the control module according to an electrostatic discharge event on the first power line of the first power source, and the control module then controls the clamping module to couple the first power line of the first power source to the second power line of the first power source;
• wherein the detection module comprises at least one diode and a first transistor, a first terminal of the first transistor is coupled with the first power line of the first power source via said at least one diode, a second terminal of the first transistor is coupled to the voltage division terminal, and a third terminal of the first transistor is coupled to the first power line of the second power source.