Chip on carrier

A chip on a carrier, comprising:

• a first substantially planar isolation layer with a first surface and a second surface opposite the first surface;
• a first substantially planar conduction layer with a first surface and a second surface opposite the first surface, the first surface of the first conduction layer positioned adjacent to the second surface of the first isolation layer;
• a second substantially planar isolation layer with a first surface and a second surface opposite the first surface, the first surface of the second isolation layer positioned adjacent to the second surface of the first conduction layer;
• a second conduction layer etched on the second surface of the second isolation layer, the second conduction layer including:
• an anode trace;
• a cathode trace;
• and an optical transmitter positioned on the cathode trace;
• and one or more vias through the second isolation layer electrically coupling the anode trace with the first conduction layer;
• wherein the anode trace comprises a substantially U-shaped pattern along an outer perimeter of the second conduction layer and the cathode trace comprises a substantially O-shaped pattern inside the anode trace.

A method to manufacture a chip on a carrier, the chip on carrier comprising a first substantially planar isolation layer with a first surface and a second surface opposite the first surface, the method comprising:

• positioning a first surface of a first substantially planar conduction layer adjacent to the second surface of the first isolation layer;
• positioning a first surface of a second substantially planar isolation layer adjacent to a second surface of the first conduction layer, the second surface of the first conduction layer opposite the first surface of the first conduction layer;
• etching a second conduction layer on a second surface of the second isolation layer, the second surface of the second isolation layer opposite the first surface of the second isolation layer, etching a second conduction layer on a second surface of the second isolation layer, the second surface of the second isolation layer opposite the first surface of the second isolation layer, the second conduction layer including:
• an anode trace;
• a cathode trace;
• positioning an optical transmitter on the cathode trace;
• creating one or more vias through the second isolation layer to electrically couple the anode trace with the first conduction layer;
• and positioning a heating resistor on the second surface of the second isolation layer.