Optoelectronic semiconductor chip and method for fabricating an optoelectronic semiconductor chip

A method for producing an optoelectronic semiconductor chip comprising the steps of:

• A) Providing at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and an active layer, which is arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer,
• B) Applying an electrically conductive layer over the p-doped semiconductor layer,
• C) Applying a mask at least in regions to the electrically conductive layer,
• D) Forming the side flank, which extends laterally with respect to the n-doped semiconductor layer, to the p-doped semiconductor layer and to the active layer, with the partial steps of:
• D1) Removal of the electrically conductive layer and at least partially of the n-doped semiconductor layer, p-doped semiconductor layer and active layer in the regions which are not covered by the mask,
• D2) Withdrawal of the mask at least laterally in the direction away from the forming side flank,
• 3) Removal of the electrically conductive layer, such that the side flank is laterally spaced from the electrically conductive layer, wherein the side flank has at least two angular partial flanks, wherein the first partial flank is arranged at least in regions laterally with respect to the p-doped semiconductor layer, wherein the second partial flank is arranged at least in regions laterally with respect to the n-doped semiconductor layer, wherein the angle of the first partial flank with respect to the active layer is flatter than the angle of the second partial flank.

An optoelectronic semiconductor chip, comprising:

• at least one n-doped semiconductor layer,
• at least one p-doped semiconductor layer and
• an active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer,
• wherein an electrically conductive layer is arranged above the p-doped semiconductor layer, wherein the electrically conductive layer is designed for electrically contacting the p-doped semiconductor layer,
• wherein, laterally to the n-doped semiconductor layer, the p-doped semiconductor layer and to the active layer, a side flank is arranged, wherein the side flank comprises at least two angular partial flanks, wherein a first partial flank is arranged at least in regions laterally with respect to the p-doped semiconductor layer, wherein a second partial flank is arranged at least in regions laterally with respect to the n-doped semiconductor layer, wherein an angle of the first partial flank with respect to the active layer is flatter than an angle of the second partial flank, wherein the electrically conductive layer is laterally spaced from the side flank, and wherein the semiconductor chip tapers from the n-doped semiconductor layer towards the p-doped semiconductor layer.