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US 10,374,101 B2Granted
Memory arrays
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
Life of this patent
Estimating the term…
Abstract
In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.
Claims14
A memory array, comprising:
- a first group of series-coupled memory cells adjacent to a first semiconductor pillar, wherein memory cells of the first group of series-coupled memory cells wrap completely around the first semiconductor pillar;
- a second group of series-coupled memory cells adjacent to a second semiconductor pillar, wherein memory cells of the second group of series-coupled memory cells wrap completely around the second semiconductor pillar;
- and
- a data line between and coupled to the first semiconductor pillar and the second conductor pillar such that the first and the second semiconductor pillars extend in opposite directions from the data line;
- wherein a memory cell of the first group of series-coupled memory cells and a memory cell of the second group of series-coupled memory cells each comprise:
- a respective gate;
- a respective first dielectric stack between a first portion of the respective gate and the semiconductor pillar, wherein the respective first dielectric stack is wrapped completely around the semiconductor pillar and is to store a charge;
- and
- a respective second dielectric stack between a second portion of the respective gate and the semiconductor pillar, wherein a memory cell of the first group of series-coupled memory cells and a memory cell of the second group of series-coupled memory cells each comprise:
- a respective gate;
- a respective first dielectric stack between a first portion of the respective gate and
- a respective semiconductor pillar of the first and second semiconductor pillars,
- wherein the respective first dielectric stack is wrapped completely around the respective semiconductor pillar and is to store a charge;
- and
- a respective second dielectric stack between a second portion of the respective gate and the respective semiconductor pillar, wherein the second dielectric stack is to store a charge and is wrapped completely around the respective semiconductor pillar such that the respective second dielectric stack is separated from the respective first dielectric stack along the respective semiconductor pillar.
12 more elements
A memory array, comprising:
- a first group of series-coupled memory cells adjacent to a first semiconductor pillar, wherein memory cells of the first group of series-coupled memory cells wrap completely around the first semiconductor pillar;
- a second group of series-coupled memory cells adjacent to a second semiconductor pillar, wherein memory cells of the second group of series-coupled memory cells wrap completely around the second semiconductor pillar;
- and
- a data line between and coupled to the first semiconductor pillar and the second conductor pillar such that the first and the second semiconductor pillars extend in opposite directions from the data line.
1 more element
Dependencies are inferred from the claim text.