Programmable non-volatile memory with low off current

A device comprising:

• a non-volatile memory having a plurality of non-volatile memory cells, each non-volatile memory cell including a floating gate transistor comprising:
• a substrate including a channel region formed between a source and a drain, wherein the channel region includes a buried channel region, a first surface channel region, and a second surface channel region, and wherein the buried channel portion is interposed between the first surface channel region and the second surface channel region;
• and
• a floating gate disposed over the substrate and overlying the channel region.

A memory transistor comprising:

• a substrate including a source, a drain, and a channel region extending between the source and the drain, wherein the channel region includes first and second surface channel regions at respective first and second ends of the channel region, the first surface channel region including a first lightly doped drain (LDD) implant region, and the second surface channel region including a second LDD implant region;
• and
• a floating gate arranged over the substrate and overlying the channel region, wherein the LDD region is located under one of first and second opposite ends of the floating gate,
• wherein the channel region includes a buried channel region located under the floating gate, the buried channel region being interposed between the first and second surface channel regions.