Low parasitic capacitance and resistance finFET device

A semiconductor structure comprising:

• a plurality of silicon semiconductor fins on a substrate;
• a plurality of raised active regions, wherein each of the plurality of semiconductor fins underlies the plurality of raised active regions, wherein each raised active region of the plurality of raised active regions is disposed on sidewalls of a corresponding silicon semiconductor fin among said plurality of silicon semiconductor fins, and is laterally spaced from any other of the raised active regions, and wherein each raised active region of the plurality of raised active regions comprises angled sidewall surfaces that are not parallel or perpendicular to a topmost horizontal surface of said substrate, wherein the raised active regions of the plurality of raised active regions comprise silicon germanium (SiGe), wherein an amount of germanium in the silicon germanium is greater than 60 weight percent, wherein the raised active regions of the plurality of raised active regions do not merge with any other of the plurality of raised active regions;
• a merged metal semiconductor alloy region contacting at least said angled sidewall surfaces of at least two adjacent raised active regions wherein said semiconductor alloy region is selected from the group consisting of nickel silicide, nickel-platinum silicide and cobalt silicide;
• a gate dielectric straddling said plurality of silicon semiconductor fins having a plurality of raised active regions;
• and
• a gate electrode overlying said gate dielectric.