3D transistor having a gate stack including a ferroelectric film

A method of fabricating a three-dimensional transistor configured to operate with less than 59 mV per decade subthreshold swing at room temperature, the method comprising:

• forming a drain;
• forming a source;
• forming a channel longitudinally extending between the drain and the source;
• forming a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm;
• and
• forming a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel;
• and
• substantially matching, over an operating range of a gate voltage, a ferroelectric capacitance of the ferroelectric film to a sum of a gate to channel capacitance (CMOS) and a gate edge capacitance (CEDGE), the CEDGE resulting at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.

A 3D transistor comprising:

• a drain;
• a source;
• a channel longitudinally extending between the drain and the source;
• a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm;
• and
• a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel, the 3D transistor having a structure configured to operate with less than 59 mV per decade subthreshold swing at room temperature, the ferroelectric film having a ferroelectric capacitance substantially matched to a gate to channel capacitance (CMOS) over an operating range of a gate voltage.

A 3D transistor comprising:

• a drain;
• a source;
• a channel longitudinally extending between the drain and the source;
• a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm;
• a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel;
• an internal conductive gate positioned between the channel and the ferroelectric film, the gate in close proximity to only a portion of the internal gate and configured to reduce the effective area of the gate to internal gate ferroelectric capacitor area, the 3D transistor having a structure configured to operate with less than 59 mV per decade subthreshold swing at room temperature.