Vertical fin field effect transistor with reduced gate length variations

A method of forming a fin field effect transistor, comprising:

• forming an elevated substrate tier on a substrate, wherein the elevated substrate tier has a height from the top surface of the substrate in a range of about 10 nm to about 50 nm;
• forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer;
• forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer;
• forming a plurality of fin masks on the top surface of the fill layer and fin template layer, wherein at least one of the plurality of fin masks is over a portion of the fill layer that extends from the surface of the substrate to the bottom surface of the at least one of the plurality of fin masks, and another one of the plurality of fin masks is over the fin mesa;
• and
• removing portions of the fill layer, fin template layer, and fin mesa to form at least one dummy fin from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on each of the opposite ends of each of the one or more vertical fins from the fill layer, wherein each of the dummy fin portions extends a distance of about 20 nm to about 100 nm from an endwall of the one or more vertical fins.