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US 10,374,055 B2Granted
Buffer layer on semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Hao Hou, Wei-Yang Lee, Xiong-Fei Yu, Kuang-Yuan Hsu
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Abstract
A semiconductor device including a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region. Additionally, the semiconductor device includes a high-k dielectric layer formed over the channel region, an n-metal formed over the high-k dielectric layer and a barrier layer formed between the high-k dielectric layer and the n-metal, the barrier layer including a layer of annealed silicon.
Claims20
A semiconductor device comprising:
- a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region;
- a high-k dielectric layer over the channel region;
- an n-metal over the high-k dielectric layer, wherein the n-metal is free of silicon;
- and
- a barrier layer between the high-k dielectric layer and the n-metal, the barrier layer comprising:
- a layer of titanium silicide alloy,
- a first layer of titanium nitride,
- a second layer of titanium nitride, wherein the layer of titanium silicide alloy is between the first layer of titanium nitride and the second layer of titanium nitride, and
- a silicon layer between the second layer of titanium nitride and the layer of titanium silicide alloy.
6 more elements
A semiconductor device comprising:
- a high-k dielectric layer over a substrate;
- a first titanium nitride layer over the high-k dielectric layer;
- a titanium silicide alloy layer on the first titanium nitride layer;
- an n-metal over the high-k dielectric layer;
- a second titanium nitride layer between the titanium silicide alloy layer and the n-metal;
- and
- a silicon layer between the second titanium nitride layer and the titanium silicide alloy layer.
4 more elements
A semiconductor device comprising:
- a gate dielectric layer over a substrate;
- a cap barrier layer over the gate dielectric layer, wherein the cap barrier layer comprises titanium nitride;
- a silicide alloy layer between the cap barrier layer and the gate dielectric;
- a lower barrier layer between the gate dielectric layer and the silicide alloy layer;
- a silicon layer over the silicide alloy layer;
- an n-metal over the silicon layer, wherein an upper-most surface of the n-metal has a width greater than a width of a bottommost surface of the n-metal;
- and
- a spacer surrounding the gate dielectric layer, wherein a top surface of the spacer is substantially coplanar with a top surface of the cap barrier.
5 more elements
Dependencies are inferred from the claim text.