Reduced capacitance coupling effects in devices

A semiconductor device comprising:

• a substrate having a device region;
• a transistor gate having first and second gate sidewalls, the transistor gate disposed on the substrate in the device region, and the transistor gate including a gate dielectric layer and a gate electrode over the gate dielectric layer;
• first and second gate sidewall spacers respectively disposed on the first and second gate sidewalls, the first gate sidewall spacer including a first ferroelectric spacer and a first dielectric spacer, the second gate sidewall spacer including a second ferroelectric spacer and a second dielectric spacer, and the first and second ferroelectric spacers each extending from a top of the transistor gate to a bottom of the transistor gate;
• and
• first and second source/drain regions respectively disposed adjacent to the first and second gate sidewalls of the transistor gate,
• wherein the first and second ferroelectric spacers comprise first and second L-shaped ferroelectric spacers that respectively line the first and second gate sidewalls and a portion of the substrate adjacent to the first and second gate sidewalls, and the first and second dielectric spacers are respectively disposed on the first and second L-shaped ferroelectric spacers.