Semiconductor device and manufacturing method thereof

A manufacturing method of a semiconductor device comprising steps of:

• forming a trench at a main surface of a semiconductor wafer of a first conductivity type;
• forming a gate insulating layer along a side wall of the trench;
• embedding a gate electrode into the trench such that an upper surface of the gate electrode is to be located below the main surface of the semiconductor wafer;
• forming a second conductivity type region along the side wall of the trench by introducing a second conductivity type impurity into the surface layer portion of the main surface of the semiconductor wafer in a side of the trench;
• forming a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode;
• and
• forming a first conductivity type region along the side wall of the trench in a surface layer portion of the second conductivity type region by introducing a first conductivity type impurity into the surface layer portion of the second conductivity type region via the side wall insulating layer.

A semiconductor wafer structure comprising:

• a semiconductor wafer of a first conductivity type set a first device formation region in which a first semiconductor device is to be formed and a second device formation region in which a second semiconductor device is to be formed, and having a main surface at which trenches are formed in each of the first device formation region and the second device formation region;
• wherein the first device formation region and the second device formation region each include
• a gate insulating layer formed along a side wall of the trench,
• a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor wafer,
• a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, and
• a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween,
• wherein the upper surface of the gate electrode formed in the second device formation region is located below the upper surface of the gate electrode formed in the first device formation region, and
• the second device formation region includes a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode.