Thin film transistor array

A thin film transistor array, comprising:

• a plurality of thin film transistors each including a gate electrode formed on an insulation substrate, a source electrode and a drain electrode formed on the gate electrode via a gate insulation film and a semiconductor layer formed on a portion of the gate electrode surrounded by at least the source electrode and the drain electrode;
• a plurality of capacitors each including a capacitor electrode formed on the insulation substrate and a pixel electrode which is formed on the capacitor electrode via the gate insulation film and connected to the drain electrode, the capacitors and the thin film transistors being positioned in a plane along a first direction and a second direction perpendicular to the first direction;
• a plurality of source wirings that extend in the first direction and connect source electrodes of the thin film transistors positioned in the first direction;
• and
• a plurality of semiconductor layer connection lines that at least partially overlap the plurality of source wirings along an entirety of a length of the plurality of source wirings in the first direction, the plurality of semiconductor layer connection lines comprising a semiconductor material and extending continuously in the first direction together with the plurality of source wirings, with which the plurality of semiconductor layer connection lines at least partially overlap, to directly connect to the semiconductor layers included in different groups of the thin film transistors positioned in the first direction in channel regions, wherein
• a width of the semiconductor layer connection lines, which at least partially overlap the plurality of source wirings along the entirety of the length of the plurality of source wirings in the first direction, in non-channel regions is smaller than a width of the semiconductor layer connection lines with the semiconductor layers of the thin film transistors in the channel regions.