Thin-film transistor array substrate and manufacturing method thereof

A thin-film transistor array substrate, comprising a base plate having a surface and a thin-film transistor arrangement and a storage capacitor formed on the surface of the base plate;

• wherein the thin-film transistor arrangement comprises at least one gate terminal arranged on the surface of the base plate and at least one oxide semiconductor layer corresponding to and located above the at least one gate terminal;
• wherein the storage capacitor comprises a first electrode plate arranged on the surface of the base plate and spaced from the at least one gate terminal of the thin-film transistor arrangement to define an intermediate area of the surface of the base plate therebetween, a second electrode plate located above the first electrode plate, a gate insulation layer located between the first electrode plate and the second electrode plate and arranged on the first electrode plate, an etch stop layer located between the first electrode plate and the second electrode plate and arranged on the gate insulation layer;
• wherein the gate insulation layer has a transistor-related portion that is located on the at least one gate terminal and interposed between the at least one gate terminal and the at least one oxide semiconductor layer, a capacitor-related portion that corresponds to and is located on the first electrode plate, and an intermediate connection portion integrally connected with the transistor-related portion and the capacitor-related portion and partly arranged on the intermediate area of the surface of the base plate to extend between the thin-film transistor arrangement and the storage capacitor, wherein the capacitor-related portion of the gate insulation layer has a thickness that is smaller than a thickness of the intermediate connection portion of the gate insulation layer that is arranged on the intermediate area of the surface of the base plate and extends between the thin-film transistor arrangement and the storage capacitor, the capacitor-related portion of the gate insulation layer being located atop the first electrode plate, such that a top of the capacitor-related portion of the gate insulation layer is spaced from the surface of the base plate by a first distance that is larger than a second distance by which a top of the immediate connection portion of the gate insulation layer is spaced from the surface of the base plate;
• and
• wherein the etch stop layer is partly arranged atop the at least one oxide semiconductor layer of the thin-film transistor arrangement and extends through the intermediate area of the surface of the base plate to the first electrode plate of the storage capacitor, such that the etch stop has a first portion that is located on the capacitor-related portion of the gate insulation layer and has a top surface that is substantially consistent with a top surface of a second portion of the etch stop layer that extends from the thin-film transistor arrangement to the storage capacitor and is located on the intermediate connection portion of the gate insulation layer on the intermediate area of the surface of the base plate, the first portion and the second portion of the etch stop layer having, respectively, a first material thickness and a second material thickness that are different from each other, such that a difference between the first material thickness and the second material thickness equals to a difference between the first distance and the second distance by which the capacitor-related portion and the immediate connection portion of the gate insulation layer are spaced from the surface of the base plate in order to provide a substantially continuous flat surface between the first portion and the second portion of the etch stop layer that correspond to the capacitor-related portion and the immediate connection portion of the gate insulation layer, wherein the second electrode plate is formed on the etch top layer;
• and
• wherein a combination of the capacitor-related portion of the gate insulation layer and the first portion of the etch stop layer that are interposed between the first and second electrode plates has an overall thickness that is smaller than an overall thickness of a combination of the immediate connection portion of the gate insulation layer and the second portion of the etch stop layer that are located in the intermediate area of the surface of the base plate.