Vertical memory devices and methods of manufacturing vertical memory devices

A vertical memory device, comprising:

• a cell array including a plurality of cell regions spaced apart from each other in a second direction, each cell region of the plurality of cell regions including a regularly arranged plurality of vertical channels and at least one dummy channel;
• a plurality of bit-lines crossing the cell array in the second direction, the bit-lines being spaced apart from each other in a first direction crossing the second direction;
• and
• a plurality of bit-line contacts configured to respectively electrically connect the plurality of vertical channels to the plurality of bit-lines, wherein the plurality of vertical channels are classified into a plurality of types according to a distance in the second direction from at least one sub isolation region that isolates each of the cell regions in the second direction, and wherein the plurality of bit-line contacts are configured to electrically connect each bit-line of the plurality bit-lines to at least two vertical channels having different types in each of the cell regions.

A method of manufacturing a vertical memory device including a cell array including a plurality of cell regions spaced apart from each other in a first direction, each cell region of the plurality of cell regions including a regularly arranged plurality of vertical channels;

• a plurality of bit-lines extending in a second direction crossing the first direction, the plurality of bit-lines being spaced apart from each other in the first direction;
• and a plurality of bit-line contacts configured to respectively electrically connect the plurality of vertical channels and the plurality of bit-lines, the method comprising:
• designing a layout of the vertical memory device;
• verifying whether loads of the plurality of bit-lines are equalized in the layout;
• upon verifying that the loads of the bit-lines are equalized, manufacturing a mask for the vertical memory device;
• and
• manufacturing the vertical memory device using the mask,
• wherein the plurality of vertical channels are classified into a plurality of types according to a distance in the second direction from at least one sub isolation region that isolates each of the cell regions in the second direction, and
• wherein the plurality of bit-line contacts are configured to electrically connect each bit-line of the plurality bit-lines to at least two vertical channels having different types in each of the cell regions.