Three-dimensional memory device including partially surrounding select gates and fringe field assisted programming thereof

A three-dimensional memory device, comprising:

• a stack of alternating insulating layers and electrically conductive layers located over a substrate, wherein the electrically conductive layers comprise drain select gate electrode layers located over word line electrically conductive layers;
• memory stack structures extending through the stack in a vertical direction perpendicular to the layers and the substrate, wherein each of the memory stack structures comprises a memory film that surrounds a vertical semiconductor channel, the memory stack structures are arranged in multiple groups that are spaced apart from each other in a horizontal direction by drain select level isolation structures that each extend in the vertical direction through the drain select gate electrode layers dividing each of the drain select gate electrode layers into horizontal drain select gate electrode layer sections, and within each group of memory stack structures, at least one row of memory stack structures is arranged, each of the memory stack structures in the at least one row is only partially surrounded by a respective drain select gate electrode layer section due to each of the memory stack structures in the at least one row also directly contacting a respective one of the drain select level isolation structures;
• drain regions contacting a top end of a respective one of the vertical semiconductor channels;
• and
• bit lines that are electrically shorted to a respective subset of the drain regions such that each bit line is electrically shorted to only one drain region per each neighboring pair of groups of memory stack structures, and each bit line is electrically shorted to more than one drain region in a first memory block.

A three-dimensional memory device, comprising:

• a stack of alternating insulating layers and electrically conductive layers located over a substrate, wherein the electrically conductive layers comprise drain select gate electrode layers located over word line electrically conductive layers;
• memory stack structures extending through the stack in a vertical direction perpendicular to the layers and the substrate, wherein each of the memory stack structures comprises a memory film that surrounds a vertical semiconductor channel, wherein the memory stack structures are arranged in multiple groups that are spaced apart from each other in a horizontal direction by drain select level isolation structures that each extend in the vertical direction through the drain select gate electrode layers dividing each drain select gate electrode layer into drain select gate electrode layer sections, and wherein
• at least one row of memory stack structures is arranged, each of the memory stack structures in the at least one row is only partially surrounded by a respective drain select gate electrode layer section due to each of the memory stack structures in the at least one row also directly contacting a respective one of the drain select level isolation structures;
• and
• a control circuitry configured to provide charge injection into the memory films at the level of the drain select gate electrode layers, wherein the control circuitry comprises:
• a target string bias voltage supply circuitry configured to generate a target string bias voltage;
• a neighboring string bias voltage supply circuitry configured to generate a neighboring string bias voltage;
• a pass bias voltage supply circuitry configured to generate a pass bias voltage, wherein the neighboring string bias voltage is different from the pass bias voltage;
• a programming drain bias voltage circuitry configured to generate a programming drain bias voltage;
• and
• an address decoder and a switch circuitry that are configured:
• to apply the target string bias voltage to a selected drain select gate electrode layer section, which partially surrounds a first row of memory stack structures in a respective group of memory stack structures, wherein each of the memory stack structures of the first row is in direct contact with a first one of the drain select isolation structures;
• to apply the neighboring string bias voltage to a first unselected drain select gate electrode layer section that that neighbors the selected drain select gate electrode layer section and contacts a first one of the drain select level isolation structures;
• to apply the pass bias voltage to a second unselected drain select gate electrode layer section that is spaced from the selected drain select gate electrode layer section in the horizontal direction by the at least one select gate electrode layer section;
• and
• to apply the programming drain bias voltage to a vertical semiconductor channel within a selected memory stack structure at least partially laterally surrounded by the selected drain select gate electrode layer section.