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US 10,373,965 B2Granted
OTP cell having a reduced layout area
AssigneeMagnaChip Semiconductor, Ltd.
InventorsYoung Chul Seo, Duk Ju Jeong
Life of this patent
Estimating the term…
Abstract
An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.
Claims24
A one-time programmable (OTP) cell array, comprising:
- a deep well region of a first conductivity type disposed in a semiconductor substrate;
- a first well region and a second well region of a second conductivity type disposed next to each other and formed in the deep well region;
- a first gate electrode disposed on a first gate insulating film on the first well region of the semiconductor substrate and a second gate electrode disposed on a second gate insulating film on the second well region;
- a first well bias tap region disposed in the first well region;
- first and second doped regions disposed in the second well region;
- and
- an isolation region disposed in the semiconductor substrate,
- wherein the first well bias tap region is doped with dopants of a same conductivity type as the first well region, and
- the first and second doped regions are doped with dopants of a different conductivity type from the first well region and the second well region.
6 more elements
A one-time programmable (OTP) cell array, comprising:
- a first well region and a second well region of a first conductivity type disposed next to each other and formed in a deep well region of a second conductivity type in a semiconductor substrate, and
- a first gate electrode disposed on a first gate insulating film on the first well region and a second gate electrode disposed on a second gate insulating film on the second well region;
- a well bias tap region disposed in the first well region and doped with dopants of a same conductivity type as the first well region;
- first and second doped regions disposed in the second well region and doped with dopants of a different conductivity type from the first well region and the second well region;
- a first isolation region disposed in the semiconductor substrate;
- and
- a gate contact plug disposed on the first gate electrode,
- wherein the first gate electrode and the gate contact plug overlap with the first isolation region.
5 more elements
A one-time programmable (OTP) cell array, comprising:
- OTP cells arranged in a matrix pattern, wherein each of the OTP cells comprises a selection transistor and an anti-fuse,
- wherein the selection transistor comprises a first gate electrode disposed on a first gate insulating film on a first well region of a semiconductor substrate, and first and second doped regions disposed in the first well region,
- wherein the anti-fuse comprises a second gate electrode disposed on a second gate insulating film on a second well region,
- wherein the first and second well regions of a first conductivity type are disposed next to each other and formed in a deep well region of a second conductivity type disposed on the semiconductor substrate,
- wherein at least one OTP cell among the OTP cells comprises a first well bias tap region disposed in the second well region, and
- wherein the first well bias tap region is doped with dopants of a same conductivity type as the second well region, and the first and second doped regions are doped with dopants of a different conductivity type from the first well region and the second well region.
3 more elements
A one-time programmable (OTP) cell array, comprising:
- OTP cells arranged in a matrix pattern, wherein each of the OTP cells comprises a selection transistor and an anti-fuse,
- wherein the selection transistor comprises a first gate electrode disposed on a first gate insulating film on a first well region of a semiconductor substrate, and first and second doped regions formed in the first well region and doped with dopants of a different conductivity type from the first well region,
- wherein the anti-fuse comprises a second gate electrode disposed on a second gate insulating film on a second well region of the semiconductor substrate, first and second well bias tap regions doped with dopants of a same conductivity type as the second well region, and a gate contact plug disposed on the second gate electrode,
- wherein the first well region and the second well region having a same dopant conductivity type are disposed next to each other and formed in a deep well region in the semiconductor substrate,
- wherein each of the OTP cells comprises a first isolation region disposed between the selection transistor and the anti-fuse in the semiconductor substrate, and
- wherein the second gate electrode and the gate contact plug overlap with the first isolation region.
3 more elements
A one-time programmable (OTP) cell, comprising:
- a transistor disposed in a first well region and comprising:
- a first gate insulating film disposed on a semiconductor substrate,
- a first gate electrode disposed on the first gate insulating film,
- doped regions doped with dopants of a different conductivity type from the first well region and disposed adjacent to the first gate electrode, and
- a first contact plug disposed on one of the doped regions;
- an anti-fuse disposed in a second well region disposed adjacent to the first well region and having a same conductivity type as the first well region, the anti-fuse comprising:
- a first well bias tap region doped with dopants of a same conductivity type as the second well region, the first and second well regions being disposed in a deep well region in the semiconductor substrate,
- a second gate insulating film disposed on the semiconductor substrate,
- a second gate electrode disposed on the second gate insulating film, and
- a second contact plug disposed on the second gate electrode;
- and
- an isolation region disposed between the first transistor area and the second transistor area,
- wherein the first contact plug is connected to the second contact plug by a metal layer.
10 more elements
Dependencies are inferred from the claim text.