Method for fabricating a local interconnect in a semiconductor device

A method of manufacturing a static random access memory (SRAM) cell, the SRAM cell comprising:

• a first field effect transistor (FET) having a first gate, a first source and a first drain, the first gate being coupled to a word line, the first drain being coupled to a first bit line;
• a second FET having a second gate, a second source and a second drain, the second drain being coupled to a first power supply line;
• a third FET having a third gate, a third source and a third drain, the third drain being coupled to a second power supply line;
• a fourth FET having a fourth gate, a fourth source and a fourth drain, the fourth gate being coupled to the word line, and the fourth drain being coupled to a second bit line;
• a fifth FET having a fifth gate, a fifth source and a fifth drain, the fifth drain being coupled to the first power supply line;
• a sixth FET having a sixth gate, a sixth source and a sixth drain, the sixth drain being coupled to the second power supply line, wherein:
• the second gate and the third gate share a first gate electrode layer and the fifth gate and the sixth gate share a second gate electrode layer,
• the method comprising:
• forming a first epitaxial layer over the first source and the second source, and a second epitaxial layer over the third source;
• and
• forming a first local interconnect that electrically connects the first epitaxial layer, the second epitaxial layer and the second gate electrode layer,
• wherein a portion of the first local interconnect connecting the second epitaxial layer and the second gate electrode layer has a neck portion having a width narrower than a head portion of the first local interconnect disposed over the second gate electrode layer, in a direction in which the second gate electrode extends.

A method of manufacturing a semiconductor device, the method comprising:

• forming a first gate structure and a second gate structure over a substrate, the first gate structure including a first gate electrode, a first cap insulating layer disposed over the first gate electrode and a first sidewall spacer disposed on side faces of the first gate electrode and the first cap insulating layer, the second gate structure including a second gate electrode, a second cap insulating layer disposed over the second gate electrode and a second sidewall spacer disposed on side faces of the second gate electrode and the second cap insulating layer;
• forming a first source/drain region and a second source/drain region in an area between the first sidewall spacer and the second sidewall spacer;
• forming a first insulating layer over the first and second source/drain regions and between the first sidewall spacer and the second sidewall spacer;
• after forming the first insulating layer, removing a part of the first cap insulating layer, thereby forming a first space adjacent to the first source/drain region with the first sidewall spacer interposed;
• forming a second insulating layer over the first and second gate structures and in the first space;
• removing a part of the second insulating layer and a part of the first insulating layer above the first and second source/drain regions, and further removing a part of the first sidewall spacer adjacent to the firs source/drain region, thereby forming a second space in which a part of an upper surface of the first gate electrode and the first source/drain region are exposed and a third space in which the first source/drain region are exposed;
• and
• filling the second space and the third with a conductive material, thereby connecting the first gate electrode and the first source/drain region, and forming a contact layer over the second source/drain region.