Semiconductor device including trimmed-gates and method for generating layout of same

A non-transitory, computer-readable medium comprising computer-executable instructions for carrying out a method of generating a layout of a semiconductor device, the method comprising:

• generating active area (AR) patterns arranged in a first grid oriented parallel to a first direction;
• generating gate patterns arranged spaced apart in a second grid and overlying corresponding ones of the AR patterns, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction;
• wherein gaps, which are interspersed between neighboring ones of the AR patterns, are overlied by corresponding intra-gap segments of the gate patterns, each intra-gap segment including two end regions separated by a central region;
• generating first cut-patterns which overlie the central regions of first selected ones of the intra-gap segments;
• and
• generating second cut-patterns which overlie the end regions of second selected ones of the intra-gap segments which abut flyover intersections thereby trimming the corresponding gate patterns;
• wherein:
• the first and second cut-patterns are indicative that corresponding underlying central regions and end regions will be removed subsequently;
• and
• each of the flyover intersections is an instance of an intersection at which a corresponding gate pattern intersects a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be not be functionally connected to an active region resulting from the corresponding AR pattern.

A method of generating a layout of a semiconductor device , the layout being stored on a non-transitory computer-readable medium, the method comprising:

• generating active area (AR) patterns arranged in a first grid oriented parallel to a first direction;
• generating gate patterns arranged spaced apart in a second grid and overlying corresponding ones of the AR patterns, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction;
• wherein gaps, which are interspersed between neighboring ones of the AR patterns, are overlied by corresponding intra-gap segments of the gate patterns, each intra-gap segment including two end regions separated by a central region;
• generating first cut-patterns which overlie the central regions of first selected ones of the intra-gap segments;
• generating second cut-patterns which overlie the end regions of second selected ones of the intra-gap segments which abut flyover intersections thereby trimming the corresponding gate patterns;
• substantially aligning, relative to the first direction, midlines of the second cut-patterns over centerlines of the corresponding gate patterns;
• and
• wherein:
• the first and second cut-patterns are indicative that corresponding underlying central regions and end regions will be removed subsequently;
• each of the flyover intersections is an instance of an intersection at which a corresponding gate pattern crosses over a corresponding AR pattern and for which a gate electrode resulting from the corresponding gate pattern will be not be functionally connected to an active region resulting from the corresponding AR pattern;
• and
• at least one of the generating AR patterns, generating gate patterns, generating first cut-patterns or generating second cut-patterns is executed by a processor of a computer.