Semiconductor device having a multi-thickness gate trench dielectric layer

A semiconductor device, comprising:

• a semiconductor substrate having a gate trench comprised of an upper trench and a lower trench, wherein the upper trench is wider than the lower trench;
• a gate embedded in the gate trench, wherein the gate comprises an upper portion and a lower portion;
• a first gate dielectric layer between the upper portion and the upper trench, wherein the first gate dielectric layer has a first thickness;
• and
• a second gate dielectric layer between the lower portion and the lower trench, wherein the second gate dielectric layer has a second thickness that is smaller than the first thickness, wherein the gate comprises a tungsten layer and TiN liner layer, wherein the TiN liner layer is disposed between the tungsten layer and the first gate dielectric layer and between the tungsten layer and the second gate dielectric layer.