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US 10,373,942 B2Granted
Logic layout with reduced area and method of making the same
AssigneeGlobalfoundries Inc.
InventorsRam Asra, Mohit Bajaj, Edward Nowak, Kota V. R. M. Murali
Life of this patent
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Abstract
A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.
Claims10
A method comprising:
- forming a first field effect transistor (FET) over a substrate;
- forming an insulating material over the first FET;
- forming a second FET over the insulating material;
- patterning the first FET, insulating material and second FET to form fins over the substrate of a static random-access memory (SRAM) cell, a negated or (NOR) flash memory cell or a negative-and (NAND) flash memory cell;
- forming an insulating material between the substrate and the PFET;
- forming shallow trench isolation (STI) regions between the fins;
- forming a dummy gate over the fins;
- removing the NFET and insulating material from a portion of the fins down the PFET not covered by the dummy gate;
- forming a dielectric layer over the substrate and removing a portion of the dielectric layer down to the PFET not covered by the dummy gate;
- forming a spacer on side surfaces of the dummy gate;
- removing the dielectric layer;
- removing the PFET not covered by the dummy gate to form a PFET junction cavity between the insulating material and spacer;
- forming silicon germanium (SiGe) in the PFET junction cavity to form p+ source/drain (S/D) regions;
- removing the spacer from the dummy gate;
- forming a second dielectric over the substrate;
- removing a portion of the second dielectric layer down to the NFET covered by the dummy gate to form a NFET junction cavity;
- forming silicon phosphorous (SiP) in the NFET junction cavity to form n+ S/D regions;
- removing the second dielectric layer;
- and
- performing silicidation of the p+ S/D regions and n+ S/D regions,
- wherein a p-channel is formed between the p+ S/D regions under the dummy gate and an n-channel is formed between the n+ S/D regions under the dummy gate, and
- wherein the first FET is a p-channel FET (PFET) and the second FET is a n-channel FET (NFET), or the first FET is a NFET and the second FET is a PFET.
19 more elements
A method comprising:
- forming a first field effect transistor (FET) over a substrate;
- forming an insulating material over the first FET;
- forming a second FET over the insulating material;
- patterning the first FET, insulating material and second FET to form fins over the substrate;
- forming an insulating material between the substrate and the first FET;
- forming isolation regions between the fins;
- forming a dummy gate over the fins;
- removing the second FET and insulating material from a portion of the fins down the first FET not covered by the dummy gate;
- forming a dielectric layer over the substrate and removing a portion of the dielectric layer down to the first FET not covered by the dummy gate;
- forming a spacer on side surfaces of the dummy gate;
- removing the dielectric layer;
- removing the first FET not covered by the dummy gate to form a first FET junction cavity between the insulating material and spacer;
- forming first source/drain (S/D) regions in the first FET junction cavity;
- removing the spacer from the dummy gate;
- forming a second dielectric over the substrate;
- removing a portion of the second dielectric layer down to the second FET covered by the dummy gate to form a second FET junction cavity;
- forming second S/D regions in the second FET junction cavity;
- and
- removing the second dielectric layer.
16 more elements
Dependencies are inferred from the claim text.