Stacked semiconductor package

A stacked semiconductor package comprising:

• a base substrate layer;
• a sub semiconductor package disposed on a top surface of the base substrate layer, the sub semiconductor package comprising:
• a plurality of sub semiconductor chips spaced horizontally apart from one another,
• a sub mold layer filling spaces between the plurality of sub semiconductor chips to surround side surfaces of the plurality of sub semiconductor chips, and
• a redistribution structure provided on active surfaces of the plurality of sub semiconductor chips and on the sub mold layer, the redistribution structure comprising redistribution pads electrically connected to the base substrate layer and a redistribution conductive layer configured to connect at least some of the plurality of sub semiconductor chips with the redistribution pads;
• and
• at least one main semiconductor chip stacked on the sub semiconductor package, the at least one main semiconductor chip electrically connected to the base substrate layer through first electrical connection members.