Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsSun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
Claims20
A semiconductor package comprising:
- a first semiconductor chip including a first through-electrode;
- a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip, at least one of the plurality of second semiconductor chips including a second through-electrode;
- a plurality of first connection bumps attached to a bottom surface of the first semiconductor chip, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer;
- and
- a plurality of second connection bumps between the first semiconductor chip and a lowermost second semiconductor chip and between adjacent two second semiconductor chips among the plurality of second semiconductor chips, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer,
- wherein the first pillar structure comprises a first pillar layer, a diffusion barrier layer, and an adhesive layer, and the second pillar structure comprises a second pillar layer and does not comprise a layer corresponding to the adhesive layer.
A semiconductor package comprising:
- a first semiconductor chip including a first through-electrode;
- a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip, at least one of the plurality of second semiconductor chips including a second through-electrode;
- a plurality of first connection bumps attached to a bottom surface of the first semiconductor, chip, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer, the first pillar structure including a first pillar layer and a diffusion barrier layer, a diameter of the first pillar layer being smaller than that of the diffusion barrier layer;
- and
- a plurality of second connection bumps between the first semiconductor chip and a lowermost second semiconductor chip and between adjacent two second semiconductor chips among the plurality of second semiconductor chips, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer.
Dependencies are inferred from the claim text.