Replacement metal gate processes for vertical transport field-effect transistor

A method of forming a semiconductor structure, comprising:

• forming a plurality of fins disposed over a top surface of a substrate;
• and
• forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process;
• wherein a gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin;
• wherein forming the one or more VTFETs comprises:
• forming bottom source/drain regions disposed over the top surface of the substrate surrounding the plurality of fins;
• forming bottom spacers disposed over the bottom source/drain regions;
• forming an oxide layer disposed over the bottom spacers and sidewalls of the plurality of fins;
• forming a dummy gate disposed over the oxide layer;
• recessing the dummy gate below top surfaces of the plurality of fins;
• removing exposed portions of the oxide layer;
• forming top spacers disposed over the dummy gate and the plurality of fins;
• wherein the dummy gate comprises a shared dummy gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:
• a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device;
• and
• a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device;
• and
• wherein forming the one or more VTFETs further comprises:
• patterning a gate opening in an interlevel dielectric layer disposed over a top spacer disposed over the shared dummy gate;
• removing portions of the interlevel dielectric layer to expose a portion of the top surface of the top spacer;
• forming a liner on exposed sidewalls of the interlevel dielectric layer in the gate opening;
• and
• removing the shared dummy gate.

A semiconductor structure, comprising:

• a substrate;
• and
• a plurality of fins disposed over a top surface of the substrate, the plurality of fins comprising channels for one or more vertical transport field-effect transistors (VTFETs) formed with a replacement metal gate (RMG) process;
• wherein a given one of the VTFETs comprises a gate surrounding at least one of the plurality of fins, the gate of the given VTFET comprising a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin;
• a bottom source/drain region disposed over the top surface of the substrate surrounding the plurality of fins;
• a bottom spacer disposed over the bottom source/drain region;
• the gate surrounding the plurality of fins;
• a top spacer disposed over the gate;
• top source/drain regions disposed over a portion of the top spacer disposed over each of the plurality of fins;
• top source/drain contact metal layers disposed over the top source/drain regions;
• top source/drain SAC capping layers disposed over the top source/drain metal contact layers;
• a bottom source/drain contact metal layer disposed over a portion of the bottom source/drain region;
• and
• a bottom source/drain SAC capping layer disposed over the bottom source/drain metal contact layer;
• wherein the gate of the given VTFET comprises a shared gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:
• a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device;
• and
• a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device.

An integrated circuit comprising:

• one or more vertical transport field-effect transistors (VTFETs) comprising:
• a substrate;
• and
• a plurality of fins disposed over a top surface of the substrate, the plurality of fins comprising channels for the one or more VTFETs formed with a replacement metal gate (RMG) process;
• wherein a given one of the VTFETs comprises a gate surrounding at least one of the plurality of fins, the gate of the given VTFET comprising a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin;
• wherein the one or more VTFETs further comprise:
• a bottom source/drain region disposed over the top surface of the substrate surrounding the plurality of fins;
• a bottom spacer disposed over the bottom source/drain region;
• the gate surrounding the plurality of fins;
• a top spacer disposed over the gate;
• top source/drain regions disposed over a portion of the top spacer disposed over each of the plurality of fins;
• top source/drain contact metal layers disposed over the top source/drain regions;
• top source/drain SAC capping layers disposed over the top source/drain metal contact layers;
• a bottom source/drain contact metal layer disposed over a portion of the bottom source/drain region;
• and
• a bottom source/drain SAC capping layer disposed over the bottom source/drain metal contact layer;
• wherein the gate of the given VTFET comprises a shared gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:
• a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device;
• and
• a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device.