US 10,373,910 B2 · Metal alloy capping layers for metallic interconnect structures

Abstract

A semiconductor device is provided which comprises a metal interconnect structure having a metal alloy capping layer formed within a surface region of the metal interconnect structure, as well as methods for fabricating the semiconductor device. For example, a method comprises forming a metal interconnect structure in a dielectric layer, and applying a surface treatment to a surface of the metal interconnect structure to form a point defect layer in the surface of the metal interconnect structure. A metallic capping layer is then formed on the point defect layer of the metal interconnect structure, and a thermal anneal process is performed to convert the point defect layer into a metal alloy capping layer by infusion of metal atoms of the metallic capping layer into the point defect layer. The resulting metal alloy capping layer comprises an alloy of metallic materials of the metal capping layer and the metal interconnect structure.

Claims19

Dependent claims

A semiconductor device, comprising:

a metal interconnect structure disposed in a dielectric layer, wherein the metal interconnect structure comprises a first metallic material, and wherein the dielectric layer comprises an upper densified surface layer;
a metallic capping layer disposed on a surface of the metal interconnect structure, wherein the metallic capping layer comprises a second metallic material;
and
a metal alloy capping layer integrally disposed within an upper surface region of the metal interconnect structure, wherein an upper surface of metal alloy capping layer is coplanar with the upper densified surface layer of the dielectric layer;
wherein the metal alloy capping layer comprises an alloy of the first metallic material of the metal interconnect structure and the second metallic material of the metallic capping layer;
and
wherein the metal alloy capping layer comprises metallic atoms of the second metallic material of the metallic capping layer infused into vacancy point defects within a layer of vacancy point defects formed in the upper surface region of the metal interconnect structure.

4 more elements

A semiconductor device, comprising:

a metal interconnect structure disposed in a dielectric layer, wherein the metal interconnect structure comprises a first metallic material, and wherein the dielectric layer comprises an upper densified surface layer;
a metallic capping layer disposed on a surface of the metal interconnect structure, wherein the metallic capping layer comprises a second metallic material;
and
a metal alloy capping layer integrally disposed within an upper surface region of the metal interconnect structure, wherein an upper surface of metal alloy capping layer is coplanar with the upper densified surface layer of the dielectric layer;
wherein the metal alloy capping layer comprises an alloy of the first metallic material and the second metallic material;
wherein the metal alloy capping layer comprises metallic atoms of the second metallic material of the metallic capping layer infused into vacancy point defects within a layer of vacancy point defects formed in the upper surface region of the metal interconnect structure;
wherein the metal alloy capping layer comprise a first sublayer and a second sublayer;
wherein the first sublayer comprises a first concentration of atoms of the second metallic material of the metallic capping layer infused into the vacancy point defects in the upper surface region of the metal interconnect structure;
wherein the second sublayer comprises a second concentration of atoms of the second metallic material of the metallic capping layer infused into the vacancy point defects in the upper surface region of the metal interconnect structure;
and
wherein the first concentration of atoms of the second metallic material is greater than the second concentration of atoms of the second metallic material.

8 more elements

Dependencies are inferred from the claim text.

Metal alloy capping layers for metallic interconnect structures

Life of this patent

Metal alloy capping layers for metallic interconnect structures

Life of this patent

Abstract

Claims19