Semiconductor device and method of packaging

A semiconductor device comprising:

• a semiconductor die comprising four side surfaces and an active surface, the semiconductor die further comprising contact pads disposed over the active surface;
• conductive interconnects comprising first ends coupled to the contact pads and second ends opposite the first ends;
• a single encapsulant contacting the four side surfaces of the semiconductor die and side surfaces of the conductive interconnects, the single encapsulant further comprising a planar surface disposed over the active surface of the semiconductor die, the planar surface being offset from the active surface by more than the height of the conductive interconnects;
• openings formed through the planar surface of the single encapsulant and extending to the second ends of the conductive interconnects, the openings comprising a depth greater than or equal to 1 micrometers (μm);
• and
• a build-up interconnect layer disposed over the planar surface and comprising a fan-out redistribution layer (RDL) extending into the openings to electrically connect with the conductive interconnects.

A semiconductor device comprising:

• a semiconductor die comprising an active surface and contact pads disposed over the active surface;
• conductive interconnects comprising first ends coupled to the contact pads and second ends opposite the first ends;
• an encapsulant comprising a planar surface disposed over the active surface of the semiconductor die, the encapsulant comprising openings with a distance greater than or equal to 1 micrometer (μm) that extend from the planar surface of the encapsulant to the conductive interconnects;
• and
• a build-up interconnect layer disposed over the planar surface and comprising a fan-out redistribution layer (RDL) extending across the planar surface of the encapsulant and into the openings to electrically connect with the conductive interconnects.