Dynamic random access memory with low leakage current and related manufacturing method thereof

A dynamic random access memory with low leakage current, comprising:

• a substrate;
• a plurality of gates formed within the substrate;
• a plurality of drain/sources, wherein the plurality of drain/sources are formed within the substrate by a first ion implantation;
• and
• a plurality of lightly doped drains, wherein the plurality of lightly doped drains are formed under all of the plurality of drain/sources or partial drain/sources of the plurality of drain/sources by a second ion implantation, wherein the plurality of lightly doped drains is used for reducing a leakage current within the dynamic random access memory, and the second ion implantation has a predetermined incident angle;
• wherein an upper surface of each lightly doped drain of the plurality of lightly doped drains is connected to a partial lower surface of a corresponding drain/source on the each lightly doped drain.

A dynamic random access memory with low leakage current, comprising:

• a substrate;
• a plurality of gates formed within the substrate;
• a plurality of drain/sources, wherein the plurality of drain/sources are formed within the substrate by a first ion implantation;
• and
• a plurality of lightly doped drains, wherein the plurality of lightly doped drains are formed under all of the plurality of drain/sources or partial drain/sources of the plurality of drain/sources by a second ion implantation, wherein the plurality of lightly doped drains is used for reducing a leakage current within the dynamic random access memory, an upper surface of each lightly doped drain of the plurality of lightly doped drains is connected to a partial lower surface of a corresponding drain/source on the each lightly doped drain.

A dynamic random access memory with low leakage current, comprising:

• a substrate;
• a plurality of gates formed within the substrate;
• a plurality of drain/sources formed within the substrate;
• and
• a plurality of lightly doped drains, wherein lightly doped drains are formed on side walls of two adjacent gates, and the lightly doped drains are under corresponding drain/sources;
• wherein an upper surface of each lightly doped drain of the plurality of lightly doped drains is connected to a partial lower surface of a corresponding drain/source on the each lightly doped drain.

A dynamic random access memory with low leakage current, comprising:

• a substrate;
• a plurality of gates formed within the substrate;
• a plurality of drain/sources formed within the substrate;
• a plurality of isolation layers formed within the substrate, and each isolation layer is located between two gates;
• and
• a plurality of lightly doped drains, wherein lightly doped drains are formed on side walls of the two gates facing the each isolation layer and side walls of the each isolation layer, and the lightly doped drains are under corresponding drain/sources;
• wherein an upper surface of each lightly doped drain of the plurality of lightly doped drains is connected to a partial lower surface of the a corresponding drain/source on the each lightly doped drain.