Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors

A method, comprising:

• receiving an erase command;
• and
• in response to the erase command:
• charging up a channel of a set of memory cells while applying control gate voltages to the memory cells erase the memory cells, the set of memory cells comprises a dummy memory cell positioned adjacent to a select gate transistor, the set of memory cells also comprises a data memory cell;
• and
• after the erasing, providing a control gate-to-channel voltage for the dummy memory cell which is greater than a control gate-to-channel voltage for the data memory cell.

An apparatus, comprising:

• means for erasing a set of memory cells in an erase loop of a multi-loop erase operation;
• and
• means for selectively programming one or more memory cells of the set of memory cells positioned adjacent to select gate transistors, during the erase loop;
• wherein:
• the set of memory cells are in a NAND chain;
• a bottom of the NAND chain is connected to a substrate;
• and
• the means for erasing comprises means for applying an erase pulse to the substrate, and means for applying a control gate voltage to the one or more memory cells while the erase pulse is applied to the substrate, wherein the control gate voltage applied to the one or more memory cells is incremented over the erase loops of the erase operation.

An apparatus, comprising:

• a plurality of sets of connected transistors arranged in a block, each set of connected transistors comprising a data memory cell, a dummy memory cell and a select gate transistor adjacent to the select gate transistor, each set of connected transistors comprising a continuous channel;
• circuitry configured to inject holes into the channels in an erase loop of an erase operation;
• and
• circuitry configured to selectively inject electrons into portions of the channels within the dummy memory cells in the erase loop.

A system, comprising:

• a controller;
• a substrate;
• a NAND chain comprising a select gate transistor, a dummy memory cell adjacent to the select gate transistor and a data memory cell, a bottom of the NAND chain is in contact with the substrate;
• a first voltage driver connected to the substrate;
• a second voltage driver connected to the dummy memory cell;
• and
• a third voltage driver connected to the data memory cell;
• the controller, in response to an erase command for the data memory cell, is configured to instruct the first voltage driver to apply an erase pulse to the substrate, instruct the second voltage driver to apply a control gate voltage to the dummy memory cell at a level which causes erasing while the erase pulse is applied to the substrate, and instruct the third voltage driver to apply a control gate voltage to the data memory cell at a level which causes erasing while the erase pulse is applied to the substrate, and after the erase pulse is applied to the substrate, the controller is configured to apply a control gate voltage to the dummy memory cell at a level which causes programming.