Nonvolatile memory device and operating method of the same

A method of operating a nonvolatile memory device, the method comprising:

• applying a read voltage to a first word line of a plurality of word lines connected to a first memory cell of a plurality of memory cells;
• pre-charging a first bit line of a plurality of bit lines connected to the first memory cell;
• charging a sensing node connected to the first bit line to a first voltage;
• developing a voltage level of the sensing node through the first bit line based on data state of the first memory cell;
• latching first read data at a first time point by developing the voltage level of the sensing node;
• latching second and third read data at second and third time points, respectively by developing the voltage level of the sensing node, wherein the first to third time points are different from each other;
• generating a fourth read data based on the second and third read data;
• and
• selectively outputting the fourth read data as an output data depending on whether an error correction of the first read data is possible.

A nonvolatile memory device comprising:

• a cell array including a plurality of memory cells configured to store program data;
• and
• a page buffer including a plurality of page buffer units each connected to a set of the plurality of memory cells through one bit line of a plurality of bit lines connected to a sensing node, and configured to generate output data based on data states of the set of the plurality of memory cells,
• wherein a first page buffer unit of the plurality of page buffer units includes:
• first to third latches configured to, in response to a single read command received from a memory controller, latch first to third read data at first to third time points, respectively by developing a voltage level of the sensing node based on data state of a selected memory cell, wherein the first to third time points are different from each other, and
• a fourth latch configured to generate a fourth read data based on the second and third read data,
• wherein the first page buffer unit is configured to selectively output the fourth read data as the output data, depending on whether an error correction of the first read data is possible by an error correction code (ECC) circuit.