US 10,373,689 B2 · Semiconductor memory device and method of operating the same

Abstract

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform an erase operation on a selected memory block. The control circuit may control the peripheral circuit such that, during the erase operation, when the selected memory block has passed an erase verification, an additional erase verification operation is performed on memory cells coupled to a reference word line among a plurality of word lines coupled to the selected memory block, and the erase operation is performed according to a result of the additional erase verification operation for the memory cells coupled to the reference word line.

Claims19

Dependent claims

A semiconductor memory device comprising:

a plurality of memory cells included in a plurality of memory blocks, respectively;
a peripheral circuit configured to perform an erase operation on a selected memory block among the plurality of memory blocks;
and
a control circuit configured to control the peripheral circuit to perform an additional erase verification operation, when threshold voltages of all memory cells included in the selected memory block have reached an erase state, on memory cells coupled to a reference word line among a plurality of word lines coupled to the selected memory block, and to perform an additional erase operation according to a result of the additional erase verification operation for the memory cells coupled to the reference word line included in the selected memory block,
wherein the control circuit is configured to designate a word line to be selected first to be the reference word line according to a predetermine program sequence, and
wherein the additional erase verification operation is performed on less than all of the plurality of word lines.

3 more elements

A method of operating a semiconductor memory device, comprising:

performing an erase operation on a plurality of memory cells included in a selected memory block among a plurality of memory blocks using a first step voltage;
performing a first verify operation using a first verify voltage to check whether an erase operation of the selected memory block has been completed;
performing a second verify operation according to a result of the first verify operation to check whether threshold voltages of memory cells coupled to a reference word line have reached the first verify voltage;
and
performing an additional erase operation on the plurality of memory cells included in the selected memory block using an erase condition determine by a result of the second verify operation,
wherein the reference word line is a word line of a plurality of word lines which is designated to be selected first according to a predetermine program sequence of the selected memory block, and
wherein the second verify operation is performed on less than all of the plurality of word lines.

4 more elements

A method of operating a semiconductor memory device, comprising:

performing an erase operation on a plurality of memory cells included in a selected memory block among a plurality of memory blocks using a first duration time of an erase voltage;
performing a first verify operation using a first verify voltage to check whether an erase operation of the selected memory block has been completed;
performing a second verify operation according to a result of the first verify operation to check whether threshold voltages of memory cells coupled to a reference word line have reached the first verify voltage;
and
performing an additional erase operation on the plurality of memory cells included in the selected memory block using an erase condition determine by a result of the second verify operation,
wherein the reference word line is a word line of a plurality of word lines which is designated to be selected first according to a predetermine program sequence of the selected memory block, and
wherein the second verify operation is performed on less than all of the plurality of word lines.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device and method of operating the same

Life of this patent

Semiconductor memory device and method of operating the same

Life of this patent

Abstract

Claims19