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US 10,373,688 B2Granted
High voltage architecture for non-volatile memory
AssigneeLongitude Flash Memory Solutions Ltd.
InventorsBogdan I. Georgescu, Gary P. Moscaluk, Vijay Raghavan, Igor G. Kouznetsov
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Abstract
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
Claims18
A method comprising:
- applying, during an erase operation, a first high voltage signal (VPOS) to a common source line (CSL) and bit line (BL), wherein the CSL and BL are coupled to a non-volatile memory (NVM) cell of a first row of NVM cells of a memory device, wherein the CSL is shared among the NVM cell and one or more other NVM cells of the first row of NVM cells in a direction of the first row;
- applying, during a program operation, a second high voltage signal (VNEG) to a word line (WL) and to a substrate line (SPW), wherein the WL and SPW are coupled to the NVM cell;
- and
- applying a third high voltage signal to the CSL during the program operation, wherein the first high voltage signal is above a highest voltage of a power supply, wherein the second high voltage signal is below a lowest voltage of a ground supply of the memory device, and wherein the third high voltage signal is different than the second high voltage signal.
1 more element
A system, comprising:
- a plurality of non-volatile memory (NVM) cells in a sector, each of the plurality of NVM cells coupled to a common source line (CSL);
- a local bit line (BL) coupled to at least one NVM cell of the plurality of NVM cells;
- a word line (WL) coupled to the at least one NVM cell;
- and
- a sector select circuit, coupled to a column of NVM cells in the sector, comprising at least one transistor disposed between the BL and a common line (CL), the sector select circuit to control a bit line voltage applied to the BL, the sector select circuit comprising:
- a first N-channel metal oxide semiconductor field-effect transistor (nMOSFET) comprising a first gate, a first well, a first source, and first drain coupled to the local bit line;
- a second nMOSFET comprising a second gate, a second well, a second drain, and second source coupled to the local bit line;
- and
- a P-channel metal oxide semiconductor field-effect transistor (pMOSFET) comprising a third gate, a third well, a third drain, and third source coupled to the local bit line.
6 more elements
A method comprising:
- performing a pre-programming operation on an NVM cell coupled to at least one transistor disposed between a bit line and a common line (CL), the at least one transistor comprising:
- a first N-channel metal oxide semiconductor field-effect transistor (nMOSFET) comprising a first gate, a first well, a first source, and first drain coupled to a local bit line;
- a second nMOSFET comprising a second gate, a second well, a second drain, and second source coupled to the local bit line;
- and
- a P-channel metal oxide semiconductor field-effect transistor (pMOSFET) comprising a third gate, a third well, a third drain, and third source coupled to the local bit line;
- wherein performing the pre-programming operation on the NVM cell comprises:
- applying a first high voltage signal (VPOS) to a first word line (WLS) coupled to the NVM cell;
- applying a second high voltage signal (VNEG) to a second word line (WL) and to a substrate line (SPW) coupled to the NVM cell;
- and
- applying a third high voltage signal (VNEG3) to a common source line (CSL) coupled to the NVM cell, wherein the common source line is shared among NVM cells of a sector of NVM cells, and the first high voltage signal is above a highest voltage of a power supply of a memory device.
7 more elements
Dependencies are inferred from the claim text.