Content addressable memory device having electrically floating body transistor
AssigneeZeno Semiconductor, Inc.
InventorsBenjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
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Abstract
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.
Claims22
A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:
- a first floating body transistor;
- a second floating body transistor;
- and
- a third transistor;
- wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node;
- wherein said third transistor is electrically connected to said common node;
- and
- wherein said first floating body transistor and said second floating body transistor store complementary data.
A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:
- a first bi-stable floating body transistor;
- and
- a second bi-stable floating body transistor;
- wherein said first bi-stable floating body transistor and said second bi-stable floating body transistor are electrically connected in series through a common node;
- and
- wherein said first floating body transistor and said second floating body transistor store complementary data.
A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:
- a first transistor having a first floating body;
- a second transistor having a second floating body;
- a third transistor;
- a first drain region contacting said first floating body;
- a second drain region contacting said second floating body;
- a first source region contacting said first floating body, spaced apart from said first drain region;
- and
- a second source region contacting said second floating body, spaced apart from said second drain region;
- wherein said first and second drain regions are electrically connected to each other;
- wherein said third transistor is electrically connected to said first and second drain regions;
- and
- wherein said first floating body and said second floating body store complementary charge states.
Dependencies are inferred from the claim text.