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US 10,373,672 B2Granted
Command signal clock gating
AssigneeMicron Technology, Inc.
InventorParthasarathy Gajapathy
Life of this patent
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Abstract
A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.
Claims6
A semiconductor device, comprising:
- a synchronous digital circuit configured to receive command address signals, wherein the synchronous digital circuit comprises a clock gating tree, comprising:
- a first clock gating stage comprising a first flip-flop configured to be latched based on a clock signal;
- and
- a second clock gating stage comprising a plurality of second flip-flops, wherein the plurality of second flip-flops are configured to be latched in response to an activate detection signal latched by the first flip-flop based on the clock signal,
- wherein the semiconductor device comprises a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device.
2 more elements
A semiconductor device, comprising:
- a synchronous digital circuit configured to receive command address signals, wherein the synchronous digital circuit comprises a clock gating tree, comprising:
- a first clock gating stage comprising a first flip-flop configured to be latched based on a clock signal;
- and
- a second clock gating stage comprising a plurality of second flip-flops, wherein the plurality of second flip-flops are configured to be latched in response to an activate detection signal latched by the first flip-flop based on the clock signal, wherein each of the command address signals comprises a two-cycle command.
1 more element
Dependencies are inferred from the claim text.