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US 10,373,671 B1Granted
Techniques for clock signal jitter generation
AssigneeMicron Technology, Inc.
InventorTyler J. Gomm
Life of this patent
Estimating the term…
Abstract
A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signals, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.
Claims20
A device, comprising:
- an integrated circuit;
- and
- a jitter generator located on the integrated circuit, comprising:
- a random number generator configured to generate a random number in response to a clock input signal;
- delay-causing circuitry configured to receive the clock input signal, and wherein the delay-causing circuitry is configured to create a delayed clock input signal;
- and
- a phase mixer configured to receive the random number, the delayed clock input signal, and the clock input signal, and wherein the phase mixer is configured to output a clock output signal comprising the clock input signal and jitter.
4 more elements
A jitter generator, comprising:
- a first variable capacitor configured to change a first value of capacitance in response to a first control signal, wherein the first variable capacitor is configured to receive a clock-in signal;
- a second variable capacitor configured to change a second value of capacitance in response to the first control signal, wherein the second variable capacitor is configured to receive the clock-in signal;
- a delay-causing circuitry configured to couple to the second variable capacitor, wherein the delay-causing circuitry is configured to receive the clock-in signal from the second variable capacitor, and wherein the delay-causing circuitry is configured to generate a delayed clock-in signal by delaying the clock-in signal;
- a random number generator configured to receive the clock-in signal, and wherein the random number generator is configured to generate a random number in response to the clock-in signal;
- and
- a phase mixer configured to receive the random number from the random number generator, to receive the clock-in signal from the first variable capacitor, and to receive the delayed clock-in signal from the delay-causing circuitry, and wherein the phase mixer is configured to generate a clock-out signal comprising the clock-in signal and added jitter.
3 more elements
A method, comprising:
- receiving an input clock signal;
- receiving a mode selection signal indicative of an operational mode;
- delaying the input clock signal through transmission in delay-causing circuitry, wherein a delay of the input clock signal caused by the delay-causing circuitry changes a value of the delay in response to the mode selection signal;
- and
- outputting, via a jitter generator, an output clock signal comprising the input clock signal and additional jitter, wherein the output clock signal is generated in response to a random number acting to mix phases of the input clock signal and a delayed input clock signal transmitted from the delay-causing circuitry.
2 more elements
A method comprising:
- receiving an input clock signal;
- generating the random number by providing the input clock signal to pseudo-random counting circuitry, wherein the random number is represented with a plurality of bits;
- transmitting a subset of the plurality of bits to one or more capacitors configured to activate in response to the subset of the plurality of bits, wherein a capacitance value of the one or more capacitors is configured to change in response to activation;
- delaying the input clock signal through transmission in delay-causing circuitry;
- and
- outputting an output clock signal comprising the input clock signal and additional jitter, wherein the output clock signal is generated in response to a random number acting to mix phases of the input clock signal and a delayed input clock signal transmitted from the delay-causing circuitry.
3 more elements
Dependencies are inferred from the claim text.