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US 10,373,670 B1Granted
Memory device with an array timer mechanism
AssigneeMicron Technology, Inc.
InventorsZhi Qi Huang, Wei Lu Chu, Hiromasa Noda, Dong Pan
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory array including a plurality of memory cells; and an array timer coupled to the memory array, configured to generate an output timing signal based on a V-I stable input and an analog reference signal, wherein: the V-I stable input is from a bandgap supply circuit, the analog reference signal is from an analog reference block, and the output timing signal is configured to control the memory array.
Claims20
A memory device, comprising:
- a memory array including a plurality of memory cells;
- a bandgap supply circuit coupled to the memory array, the bandgap supply circuit configured to provide a V-I stable input;
- an analog reference block coupled to the memory array, the analog reference block configured to provide an analog reference signal different from an electrical ground;
- and
- an array timer coupled to the memory array, the bandgap supply circuit, and the analog reference block, the array timer configured to generate an output timing signal based on the V-I stable input and the analog reference signal, the output timing signal configured to control the memory array.
2 more elements
An array timer, comprising:
- a first capacitor configured to generate a first comparator input based on storing charge thereon using a V-I stable input from a bandgap supply circuit;
- a first comparator configured to generate a first comparator output based on comparing the first comparator input and an analog reference signal from an analog reference block, wherein the analog reference signal is different from an electrical ground;
- a second capacitor configured to generate a second comparator input based on storing charge thereon using the V-I stable input;
- a second comparator configured to generate a second comparator output based on comparing the second comparator input and the analog reference signal;
- and
- a reset-set memory element configured to generate an output timing signal including a rising edge and a falling edge, wherein the rising edge corresponds to the first comparator output and the falling edge corresponds to the second comparator output.
3 more elements
A method of operating a memory device including a memory array and an array timer, the method comprising:
- receiving, at the array timer, a V-I stable input and an analog reference signal, wherein the V-I stable input is from a bandgap supply circuit and the analog reference signal is from an analog reference block;
- using the array timer, generating an output timing signal based on the V-I stable input and the analog reference signal;
- and
- controlling the memory array using the output timing signal.
1 more element
Dependencies are inferred from the claim text.