Apparatuses and methods for compute components formed over an array of memory cells

An apparatus, comprising:

• a controller;
• a memory array coupled to the controller, comprising:
• a plurality of access transistors formed in a monocrystalline silicon base substrate material having a first concentration of doping ions;
• and
• an array of storage elements;
• compute component including a plurality of compute transistors comprising an amorphous silicon semiconductor material having a second concentration of doping ions and coupled to the array;
• and
• a plurality of metal interconnects interconnecting, the plurality of access transistors, the array, and the compute component,
• wherein the compute component is formed over the array,
• wherein the second concentration is higher than the first concentration, and
• wherein the controller is configured to cause data to be transmitted, via the plurality of metal interconnects, between the plurality of access transistors, the array, and the compute component.

A method, comprising:

• forming an array of storage elements over a base substrate material;
• forming a plurality of compute transistors comprising a semiconductor material over the array;
• doping the semiconductor material to a particular concentration of doping ions;
• and
• forming sensing circuitry in the semiconductor material.

An apparatus, comprising:

• a base substrate material;
• an array of memory cells formed over the base substrate material, wherein the array includes a plurality of access transistors comprising a first semiconductor material;
• and
• a compute component formed over and coupled to the array, wherein the compute component includes a plurality of compute transistors comprising a second semiconductor material, wherein the second semiconductor material has a lower concentration of doping ions than the first semiconductor material.

An apparatus, comprising:

• a base substrate material;
• an array of memory cells formed over the base substrate material, wherein the array includes a plurality of access transistors comprising a first semiconductor material;
• and
• a compute component formed over and coupled to the array, wherein the compute component includes a plurality of compute transistors comprising a second semiconductor material,
• wherein the base substrate material comprises a monocrystalline silicon base substrate material, the first semiconductor material comprises an amorphous silicon first semiconductor material, and the second semiconductor material comprises an amorphous silicon second semiconductor material.

An apparatus, comprising:

• a base substrate material;
• an array of memory cells formed over the base substrate material, wherein the array includes a plurality of access transistors comprising a first semiconductor material;
• and
• a compute component formed over and coupled to the array, wherein the compute component includes a plurality of compute transistors comprising a second semiconductor material,
• wherein each of the memory cells comprises:
• a first access transistor;
• a second access transistor;
• and
• a capacitor,
• wherein the first and second access transistors comprise the first semiconductor material.

An apparatus, comprising:

• a base substrate material;
• an array of memory cells formed over the base substrate material, wherein the array includes a plurality of access transistors comprising a first semiconductor material;
• a compute component formed over and coupled to the array, wherein the compute component includes a plurality of compute transistors comprising a second semiconductor material;
• and
• global metal interconnects and pads formed on the compute component.