US 10,373,665 B2 · Parallel access techniques within memory sections through section independence

Abstract

A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.

Claims17

Dependent claims

A method of operating a bank of ferroelectric memory cells having multiple sections of memory cells, comprising:

activating a first memory cell;
sensing a state of the first memory cell;
identifying a second memory cell to be activated;
determining that the second memory cell is independent of the first memory cell based at least in part on determining that sense components coupled with the second memory cell are different from sense components coupled with the first memory cell;
latching, with a latch, a row line address associated with the first memory cell;
precharging the first memory cell after latching the row line address;
and
activating the second memory cell after the first memory cell begins precharging,
wherein the precharging comprises a portion of a write-back operation.

6 more elements

A method of operating a bank of ferroelectric memory cells having multiple sections of memory cells, comprising:

activating a first memory cell;
sensing a state of the first memory cell;
identifying a second memory cell to be activated;
determining that the second memory cell is independent of the first memory cell;
identifying a delay time for activating the second memory cell in response to determining that the second memory cell is independent of the first memory cell, the delay time providing a first predetermined delay for activating the second memory cell when the second memory cell is independent of the first memory cell;
precharging the first memory cell;
and
activating the second memory cell after the delay time and while precharging the first memory cell.

5 more elements

Dependencies are inferred from the claim text.

Parallel access techniques within memory sections through section independence

Life of this patent

Parallel access techniques within memory sections through section independence

Life of this patent

Abstract

Claims17