Resistive memory device having reduced chip size and operation method thereof

A resistive memory device comprising:

• a voltage generator generating a write word line voltage according to activation of a write enable signal;
• a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output word line voltage;
• a word line power path connected to the switch circuit to receive the output word line voltage;
• and
• a word line driver driving a word line of the resistive memory device according to a voltage applied to the word fine power path,
• wherein the resistive memory device starts to receive a write command after a certain delay following the activation of the write enable signal, and a write operation is performed on the resistive memory device within an activation period of the write enable-signal in response to the received write command,
• wherein the voltage generator is a charge pump generating the write word line voltage by performing a charge pumping operation in response to the activation of the write enable signal.

A resistive memory device comprising:

• a voltage generator generating a write word line voltage according to activation of a write enable signal;
• a word line power path connected to a first node receiving the write word line voltage and a second node receiving read word line voltage in a switchable manner;
• a word line driver driving a word line of the resistive memory device according to a voltage applied to the word line power path;
• and
• control logic receiving a write command and a read command together during an activation period of the write enable signal, performing a write operation corresponding to the write command within the activation period, and performing a read operation corresponding to the read command within the same activation period.