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US 10,373,662 B2Granted
Semiconductor device having ranks that perform a termination operation
AssigneeSK hynix Inc.
InventorJae Il Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first rank and a second rank. The first rank operates in synchronization with a clock signal in response to a first rank selection signal, and the second rank operates in synchronization with the clock signal in response to a second rank selection signal. The first rank performs a termination operation without performing an internal control operation if the first rank selection signal maintains an enabled state in synchronization with a first edge and a second edge of the clock signal.
Claims29
A semiconductor device comprising:
- a first rank configured to operate in synchronization with a clock signal in response to a first rank selection signal;
- and
- a second rank configured to operate in synchronization with the clock signal in response to a second rank selection signal,
- wherein the first rank generates a command for execution of an internal control operation and a termination command for execution of a termination operation based on the first rank selection signal,
- wherein the first rank generates the termination command and terminates generation of the command when the first rank selection signal is enabled during an Nth period of the clock signal, and N is a natural number greater than or equal to 2.
2 more elements
A semiconductor device comprising:
- a first command generation circuit configured to generate a first command for execution of a first internal control operation and a first termination command for execution of a termination operation from a first pre-command, in response to a first input control signal and a first termination enable signal;
- and
- a second command generation circuit configured to generate a second command for execution of a second internal control operation and a second termination command for execution of a termination operation from a second pre-command, in response to a second input control signal and a second termination enable signal,
- wherein the first pre-command is inputted to the first command generation circuit when a logic level of the clock signal is changed from a first logic level to a second logic level and the second pre-command is inputted to the second command generation circuit when the logic level of the clock signal is changed from the second logic level to the first logic level, and
- wherein a termination of the generation of the first termination command occurs during an Nth period of the clock signal, and N is a natural number greater than or equal to 2.
2 more elements
Dependencies are inferred from the claim text.