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US 10,373,657 B2Granted
Semiconductor layered device with data bus
AssigneeMicron Technology, Inc.
InventorsChikara Kondo, Chiaki Dono
Life of this patent
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Abstract
Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.
Claims16
An apparatus comprising first and second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in at least one of the first and second semiconductor chips, the first and second semiconductor chips being configured to communicate with each other by use of data bus inversion (DBI) data that have been encoded using a DBI algorithm,
- wherein the second semiconductor chip comprises a memory cell array and a first DBI computation circuit coupled to the memory cell array,
- wherein the first DBI computation circuit is configured to receive first DBI data from the first semiconductor chip, to decode the first DBI data with the DBI algorithm, and further configured to provide the decoded first DBI data to the memory cell array,
- wherein the first DBI computation circuit is further configured to receive cell data from the memory cell array, to encode the cell data into second DBI data with the DBI algorithm, and further configured to transmit the second DBI data to the first semiconductor chip,
- wherein the first semiconductor chip comprises a second DBI computation circuit configured to receive first data from a controller, to encode the first data into the first DBI data with the DBI algorithm, and further configured to provide the first DBI data to the second semiconductor chip, responsive to an enable signal, and
- wherein the second DBI computation circuit is further configured to receive the second DBI data from the first DBI computation circuit, to decode the second DBI data into second data with the DBI algorithm, and further configured to transmit the second data to the controller, responsive to the enable signal.
2 more elements
An apparatus comprising:
- first and second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in at least one of the first and second semiconductor chips, the first and second semiconductor chips being configured to communicate with each other by use of data bus inversion (DBI) data that have been encoded using a DBI algorithm;
- and
- a data bus configured to communicate the DBI data between the first semiconductor chip and the second semiconductor chip,
- wherein the first semiconductor chip comprises a driver and receiver configured to provide first data to the data bus and further configured to receive second data from the data bus,
- wherein the second semiconductor chip comprises a driver and receiver configured to provide the second data to the data bus and further configured to receive the first data from the data bus, and
- wherein the data bus is a charge recycling bus (CRB) data bus comprising a plurality of bus lanes coupled in series between a first voltage and a second voltage lower than the first voltage, the data bus configured to transmit the data between the first semiconductor chip and the second semiconductor chip in a charge recycling technique.
3 more elements
A semiconductor device comprising:
- a plurality of input terminals configured to receive input data;
- a plurality of output terminals;
- a first terminal configured to receive a first signal associated with the input data;
- a second terminal;
- a data bus inversion (DBI) encoder coupled between the plurality of input terminals and the plurality of output terminals and supplied with a DBI enable signal, the DBI encoder being configured to:
- enable a DBI encoding operation on the input data to generate and provide first output data to the plurality of output terminals when the DBI enable signal indicates a first state;
- generate a second signal associated with the first output data when the DBI enable signal indicates the first state;
- and
- disable the DBI encoding operation on the input data to generate and provide second output data to the plurality of output terminals when the DBI enable signal indicates a second state;
- a selector circuit coupled to the first terminal, the second terminal and the DBI encoder, the selector circuit being configured to provide the second terminal with first signal when the DBI enable signal indicates the second state and with the second signal when the DBI enable signal indicates the first state;
- and
- a mode register configured to provide the DBI enable signal,
- wherein the plurality of input terminals and the plurality of output terminals are formed on a first main surface of the semiconductor device and a second main surface of the semiconductor device, respectively, and the second main surface is opposite to the first main surface,
- wherein the DBI enable signal indicates the first state when the input data is subject to DBI encoding, and
- wherein the DBI enable signal indicates the second state when the input data has been DBI encoded.
12 more elements
A semiconductor device comprising:
- a plurality of input terminals configured to receive input data;
- a plurality of output terminals;
- a first terminal configured to receive a first signal associated with the input data;
- a second terminal;
- a data bus inversion (DBI) encoder coupled between the plurality of input terminals and the plurality of output terminals and supplied with a DBI enable signal, the DBI encoder being configured to:
- enable a DBI encoding operation on the input data to generate and provide first output data to the plurality of output terminals when the DBI enable signal indicates a first state;
- generate a second signal associated with the first output data when the DBI enable signal indicates the first state;
- and
- disable the DBI encoding operation on the input data to generate and provide second output data to the plurality of output terminals when the DBI enable signal indicates a second state;
- a selector circuit coupled to the first terminal, the second terminal and the DBI encoder, the selector circuit being configured to provide the second terminal with first signal when the DBI enable signal indicates the second state and with the second signal when the DBI enable signal indicates the first state;
- and
- a DBI decoder coupled between the plurality of input terminals and the plurality of output terminals, wherein the DBI decoder is configured to:
- receive the DBI enable signal;
- generate third output data responsive to input data from the plurality of output terminals subject to DBI decoding when the DBI enable signal indicates the first state;
- generate fourth output data responsive to the input data from the plurality of output terminals not subjected to the DBI decoding when the DBI enable signal indicates the second state;
- generate a third DBI signal associated with the third output data when the DBI enable signal indicates the first state;
- and
- provide the plurality of input terminals with the third output data when the DBI enable signal indicates the first state and with the fourth output data when the DBI enable state indicates the second state.
15 more elements
A system comprising:
- a controller configured to provide at least one of first and second data, the first data being encoded using a data bus inversion (DBI) algorithm and the second data being not encoded using the DBI algorithm;
- a first chip coupled to the controller;
- a second chip coupled to the first chip;
- a data bus coupled between the first chip and the second chip, the data bus configured to transmit data from the first chip to the second chip,
- wherein the first chip is configured to:
- pass through the first data to the second chip when the controller provides the first data;
- convert the second data to third data that is encoded using the DBI algorithm when the controller provides the second data;
- and
- provide the third data to the second chip,
- wherein the second chip comprises a memory cell array and a first DBI computation circuit coupled to the data bus,
- wherein the first DBI computation circuit is configured to receive input data from the data bus, to decode the input data with the DBI algorithm, and further configured to provide the decoded input data to the memory cell array,
- wherein the first chip comprises a multiple-input signature register (MISR) and linear feedback shift register (LFSR) computation circuit coupled between the controller and the data bus, and
- wherein the MISR and LFSR computation circuit is configured to receive the at least one of the first and second data, to execute MISR and LFSR computation on the at least one of the first and second data and further configured to provide the at least one of the first and second data after MISR and LFSR computation to the data bus.
10 more elements
A system comprising:
- a controller configured to provide at least one of first and second data, the first data being encoded using a data bus inversion (DBI) algorithm and the second data being not encoded using the DBI algorithm;
- a first chip coupled to the controller;
- a second chip coupled to the first chip;
- a data bus coupled between the first chip and the second chip, the data bus configured to transmit data from the first chip to the second chip,
- wherein the first chip is configured to:
- pass through the first data to the second chip when the controller provides the first data;
- convert the second data to third data that is encoded using the DBI algorithm when the controller provides the second data;
- and
- provide the third data to the second chip,
- wherein the second chip comprises a memory cell array and a first DBI computation circuit coupled to the data bus,
- wherein the first DBI computation circuit is configured to receive input data from the data bus, to decode the input data with the DBI algorithm, and further configured to provide the decoded input data to the memory cell array,
- wherein the first chip comprises a second DBI computation circuit coupled to the data bus;
- wherein the second DBI computation circuit is further configured to receive at least one of the first and second data from the controller, to encode the second data and further configured to provide the encoded data to the second chip.
10 more elements
Dependencies are inferred from the claim text.