Memory device with a signaling mechanism

Abstract

A memory device includes a first die configured to: generate a segment set based on a source data, wherein: the source data is information corresponding to a device operation, the source data having a block length representing a number of bits therein, the segment set including at least a first segment and a second segment, the first segment and the second segment having a number of bits less than the block length, and communicate the segment set with the second die; a second die configured to process the segment set according to the device operation; and a set of inter-die connectors electrically coupling the first die and the second die, the inter-die connectors include a number of dedicated Through-Silicon-Vias (TSVs), wherein the number is less than the block length.

Dependencies are inferred from the claim text.