Semiconductor device having first memory section and second memory section stacked vertically on each other

A semiconductor device, comprising:

• a first memory section and a second memory section that are sequentially stacked in a vertical direction on a top surface of a substrate,
• wherein the first memory section comprises:
• an electrode structure including a plurality of gate electrodes that are stacked along the vertical direction on the top surface of the substrate;
• a plurality of channel structures penetrating the electrode structure;
• and
• a plurality of bit lines on the electrode structure and connected to the plurality of channel structures,
• wherein the plurality of bit lines are interposed between the electrode structure of the first memory section and the second memory section, and
• wherein the second memory section comprises a plurality of variable resistance memory cells connected to the plurality of bit lines,
• wherein each of the variable resistance memory cells comprises:
• a variable resistance element;
• and
• a select element,
• wherein one of the bit lines is connected through the select element to the variable resistance element,
• wherein the select element is interposed between one of the bit lines and the variable resistance element,
• wherein the second memory section comprises a plurality of conductive lines connected to the plurality of variable resistance memory cells, and
• wherein the plurality of variable resistance memory cells are positioned at a height from the substrate between that of the plurality of bit lines and that of the plurality of conductive lines.