Scrambling apparatus and method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKai-Chun Lin, Ku-Feng Lin, Hung-Chang Yu, Yu-Der Chih
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Abstract
A memory device is provided which comprises a memory array, a first scrambling circuit and a second scrambling circuit. The first scrambling circuit is configured to provide first scrambled data with a first scrambling pattern in response to input data. The second scrambling circuit is configured to provide second scrambled data with a second scrambling pattern in response to the first scrambled data.
Claims20
A memory device, comprising:
- a memory array configured to store a first scrambling configuration comprising an index of a data block in input data;
- a first scrambling circuit coupled to the memory array and configured to provide first scrambled data with a first scrambling pattern in response to the input data and the first scrambling configuration and store the first scrambled data into the memory array, the first scrambling configuration causing the first scrambled data to comprise a same data content as but a different data sequence from the input data;
- a second scrambling circuit coupled to the memory array and configured to provide second scrambled data with a second scrambling pattern in response to the first scrambled data in the memory array;
- a storage unit coupled to the first scrambling circuit and the second scrambling circuit and configured to store the first scrambling configuration from the memory array when an access operation is activated, and
- a first pattern generation circuit configured to provide the first scrambling pattern and the second scrambling pattern based on the first scrambling configuration and a second scrambling configuration, respectively.
A method for operating a memory array associated with a first scrambling pattern and a second scrambling pattern, the memory array being configured to store a first scrambling configuration and a second scrambling configuration, the method comprising:
- receiving input data;
- storing the first scrambling configuration and the second scrambling configuration from the memory array into a storage unit external to the memory array when the input data is received;
- generating the second scrambling pattern based on the second scrambling configuration;
- providing first data based on the second scrambling pattern in response to the input data;
- writing the first data into the memory array;
- erasing the second scrambling configuration from the memory array after writing the first data;
- generating the first scrambling pattern based on the first scrambling configuration;
- providing first scrambled data based on the first data and the first scrambling pattern in response to a read operation, and
- erasing the first scrambling configuration from the memory array after providing the first scrambled data.
A method for accessing a memory array, the memory array being configured to store a first scrambling configuration, the method comprising:
- receiving input data having a first portion and a second portion;
- storing the first scrambling configuration for the first portion from the memory array into a storage unit external to the memory array when the input data is received, the first scrambling configuration comprising a first scrambling code and an index of a data block in the first portion of the input data;
- receiving a first address of the memory array;
- generating a first scrambling pattern based on the first scrambling configuration;
- providing first scrambled data based on the first scrambling pattern in response to the first portion;
- writing the first scrambled data to the memory array at the first address;
- reading the first scrambled data from the memory array;
- providing second scrambled data based on the first scrambled data and a second scrambling pattern in response to the reading, wherein the second scrambling pattern is generated based on a second scrambling configuration;
- and
- storing the first scrambling configuration and the second scrambling configuration in the memory array after writing the first scrambled data and the second scrambled data.
Dependencies are inferred from the claim text.