Control flow integrity

A control flow integrity system comprising:

• a host device comprising:
• host processor circuitry to execute a target application,
• host memory circuitry,
• processor trace (PT) processor circuitry to capture PT data related to an executing application, and
• PT controller circuitry to configure the PT processor circuitry;
• and
• accelerator circuitry that is distinct and separate from the host device, the accelerator circuitry comprising:
• accelerator processor circuitry;
• accelerator memory circuitry that includes an accelerator control flow (CF) information store to receive CF information regarding an application prior to runtime of the application;
• processor trace (PT) decoder circuitry to receive the PT data from the host device, the PT decoder circuitry further to extract a target instruction pointer (TIP) packet from the PT data and to decode the TIP packet to yield a runtime target address;
• and
• control flow integrity (CFI) checker circuitry to determine, at runtime, whether a control flow transfer of an indirect branch instruction to the runtime target address corresponds to a control flow violation based at least in part on CF information stored in the accelerator CF information store.

A control flow integrity method comprising:

• receiving, by processor trace (PT) decoder circuitry included within accelerator circuitry, PT data from a host device that is external to the accelerator circuitry;
• extracting, by the PT decoder circuitry, a target instruction pointer (TIP) packet from the PT data;
• decoding, by the PT decoder circuitry, the TIP packet to yield a runtime target address;
• and
• determining, by control flow integrity (CFI) checker circuitry at runtime, whether a control flow transfer of an indirect branch instruction to the runtime target address corresponds to a control flow violation based at least in part on control flow (CF) information stored prior to runtime by an accelerator CF information store included in the accelerator circuitry.