Homotopy optimized parasitic extraction
AssigneeMentor Graphics Corporation
InventorSandeep Koranne
Life of this patent
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Abstract
Aspects of the disclosed technology relate to techniques of parasitic extraction. A signature for a set of geometric elements of a layout design is computed based on contour-related information. The set of geometric elements corresponds to a net of connected equipotential interconnects of a circuit design. Based on comparing the signature with signatures for sets of geometric elements that have computed parasitic element values, parasitic element values for the set of geometric elements are determined.
Claims20
One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
- receiving layout design data of an integrated circuit comprising a plurality of nets, each net being a connected group of equipotential interconnects and comprising a set of geometrical elements;
- computing a first signature of a first net of the nets based on contour-related information;
- obtaining a second signature of a second net of the nets;
- determining that the following conditions are true:
- the first signature matches a first precomputed signature of a first precomputed net;
- the second signature matches a second precomputed signature of a second precomputed net;
- and
- relative location information of the first and second nets matches relative location information of the first and second precomputed nets;
- responsive to the determining, assigning a precomputed parasitic capacitance value to the first net;
- and
- forwarding the layout design data, with the precomputed parasitic capacitance value assigned to the first net, to an electronic design automation tool for physical verification.
A method, executed by at least one processor of a computer, comprising:
- by the at least one processor of the computer:
- receiving layout design data of an integrated circuit comprising a plurality of nets, each net being a set of equipotential interconnects corresponding to a set of geometrical elements;
- computing a first signature for a first one of the nets based on contour-related information;
- and
- obtaining a second signature of a second one of the nets matching a first precomputed signature of a first precomputed net;
- determining that:
- the first signature matches a second precomputed signature of a second precomputed net;
- and
- relative location information of the first and second nets matches relative location information of the second and first precomputed nets;
- subsequent to the determining, associating a precomputed parasitic capacitance value with the first net;
- and
- forwarding the layout design data, with the associated precomputed parasitic capacitance value of the first net, to an electronic design automation tool for physical verification.
A system comprising:
- one or more processors with memory coupled thereto, the one or more processors programmed to perform a method, the method comprising:
- receiving layout design data of an integrated circuit comprising a plurality of nets, each net being a connected group of equipotential interconnects and comprising a set of geometrical elements;
- computing a first signature of a first net of the nets based on second signatures of respective geometric elements on single physical layers and on third signatures of interconnects between the single physical layers, the second signatures being based on contour-related information;
- and
- determining parasitic element values for the first net based on comparing the first signature with fourth signatures of previously computed second nets, the second nets having previously computed parasitic element values;
- and
- forwarding the layout design data, with the determined parasitic element values for the first net, to an electronic design automation tool for physical verification.
Dependencies are inferred from the claim text.